Memory Cell Word Line Layout for Stable Gate Potential

The patent divides the gate electrode lines into multiple separate lines, each serving a specific data storage cell. Instead of using a single long word line to cover multiple cells, the invention segments the gate control into individual gate electrode lines (e.g., first gate electrode line, second gate electrode line) that can be independently controlled and connected to different conductive lines, thereby reducing the power consumption and voltage drop associated with long continuous conductors.

The patent implements equipotentiality by directly connecting gate electrode lines to conductive lines with minimal intervening layers. The first gate electrode line is connected to a first conductive line, and the second gate electrode line is connected to a second conductive line, ensuring that gates at different physical locations maintain consistent electric potential despite the multi-layer structure. This direct connection approach minimizes potential differences caused by multiple interposed layers.

The patent segments the gate control architecture into multiple independent gate electrode lines rather than using fewer, longer lines. Each gate electrode line is connected to specific conductive lines (first conductive line, second conductive line, etc.), creating shorter, more localized connection paths. This segmentation reduces the likelihood and impact of manufacturing defects on overall signal transmission reliability.

The patent applies universality by using conductive lines that serve dual functions: they act as word lines for selecting data storage cells and simultaneously serve as connection paths to maintain electric potential consistency across multiple gate electrode lines. The first conductive line, second conductive line, and subsequent lines are integrated into the memory array structure, performing both control and potential reference functions, thereby reducing the need for additional dedicated potential reference lines.