Volatile Memory Cell Topology for Soft Error Upset Immunity
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Solution Overview
Problem
Volatile memory elements in integrated circuits are susceptible to soft error upsets caused by cosmic rays and radioactive impurities, leading to data corruption and performance issues, especially in remote telecommunications equipment, where repair is burdensome.
Innovation Solution
The implementation of memory elements with a pair of address transistors and four transistor pairs, forming inverter-like circuits with distributed inputs, providing redundancy to mitigate soft error upsets, and using clear lines to temporarily depower transistor pairs during clearing operations to reduce surge currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional volatile memory elements are used, then circuit area and power consumption are minimized, but the memory elements are susceptible to soft error upsets causing data corruption
Solution Approach 1:
The memory element is divided into multiple transistor pairs (first through fourth transistor pairs) with distributed inputs, where each pair contributes to the overall storage function. This segmentation provides redundancy such that a soft error affecting one segment does not necessarily corrupt the entire stored data, as the other segments maintain the correct logic state
Solution Approach 2:
The patent implements redundant transistor pairs that effectively create copies of the storage function. The first and second transistor pairs store one logic value, while the third and fourth transistor pairs store the complementary logic value. This copying approach ensures that if one copy is corrupted by a soft error, the other copy preserves the correct information
2Reliability
If redundant transistor pairs are added to improve soft error immunity, then reliability increases, but circuit area and power consumption increase
Solution Approach 1:
The patent merges the storage function into a unified bistable element where four transistor pairs work together as an integrated system. The transistor pairs are interconnected such that they share common nodes and control signals, allowing the redundant structures to provide error immunity without operating as completely independent units. This merging reduces the total power consumption compared to having separate redundant memory cells
Solution Approach 2:
The patent employs clear lines that can temporarily depower specific transistor pairs during clearing operations. By dynamically changing the power state of transistor pairs based on operational needs, the circuit consumes power only when necessary for maintaining or updating the stored logic state, rather than continuously powering all transistor pairs at full strength
3Object-generated harmful factors
If clear lines are used to depower transistor pairs during clearing, then surge currents are reduced, but the clearing operation becomes more complex
Solution Approach 1:
The clear lines are activated before the main clearing operation to temporarily depower the transistor pairs, preparing them for the upcoming state transition. This preliminary action prevents surge currents from occurring during the actual clearing by ensuring the transistor pairs are already in a low-power state ready to accept the new logic value without drawing excessive current
Data Source
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AI summary
Memory elements are provided that exhibit immunity to soft error upset events when subjected to high-energy atomic particle strikes. The memory elements may each have ten transistors including two address transistors and four transistor pairs that are interconnected to form a bistable element. Clear lines such as true and complement clear lines may be routed to positive power supply terminals and ground power supply terminals associated with certain transistor pairs. During clear operations, some or all of the transistor pairs can be selectively depowered using the clear lines. This facilitates clear operations in which logic zero values are driven through the address transistors and reduces cross-bar current surges.