Programmable Logic Memory Layout for Faster Reconfiguration
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Solution Overview
Problem
Current semiconductor devices with memory-based programmable logic devices (MPLDs) face challenges in reducing the number of storage element blocks required for logic circuits and in performing efficient data input/output operations with arithmetic processors, as well as experiencing delays in reconfiguration due to the need for rewriting truth table data.
Innovation Solution
The semiconductor device incorporates a configuration control section that uses a cache to store and decompress truth table data, allowing for efficient reconfiguration of programmable logic sections by selectively reconfiguring branch logic circuits based on arithmetic operation results, and includes input/output sections for data exchange with arithmetic processors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If storage element blocks are used as connection elements to reduce the total number of storage element blocks, then the proportion of storage elements operating as logic elements increases, but the device complexity and reconfiguration time increase due to the need to rewrite truth table data
Solution Approach 1:
The patent pre-calculates and stores optimized configuration data in a configuration data storage unit before reconfiguration is needed. When reconfiguration is required, the system retrieves pre-prepared configuration data that has already been optimized to minimize the number of storage element blocks that need to be rewritten, thereby reducing reconfiguration time while achieving the goal of minimizing storage element block usage.
Solution Approach 2:
The patent creates and stores copy-optimized configuration data in a separate configuration data storage unit. Instead of directly modifying the operational truth table data during reconfiguration, the system uses pre-generated configuration copies that are optimized for minimal storage element block changes, allowing fast reconfiguration without complex real-time calculations.
2Quantity of substance
If storage element blocks are used as connection elements, then the proportion of storage elements operating as logic elements increases, but the ease of operation decreases due to the need to rewrite truth table data for reconfiguration
Solution Approach 1:
The patent extracts the reconfiguration complexity from the operational logic by separating configuration data management from the storage element blocks themselves. The configuration data storage unit holds all reconfiguration information, allowing the storage element blocks to focus solely on their logic element function. This separation makes reconfiguration easier by providing a dedicated, optimized interface for configuration changes.
Solution Approach 2:
The patent introduces a configuration data storage unit as an intermediary between the control unit and the storage element blocks. This intermediary pre-stores optimized configuration data, simplifying the reconfiguration process by eliminating the need for complex real-time truth table rewriting. The intermediary handles the complexity of optimization, making the actual reconfiguration operation straightforward.
3Adaptability or versatility
If truth table data is rewritten for reconfiguration, then the logic circuit can be reconfigured, but the productivity decreases due to reconfiguration delays
Solution Approach 1:
The patent performs reconfiguration optimization in advance by pre-calculating and storing optimized configuration data in the configuration data storage unit. When reconfiguration is needed, the system simply retrieves pre-optimized data rather than performing complex optimization calculations in real-time, dramatically improving reconfiguration speed while maintaining full adaptability.
Solution Approach 2:
The patent combines the configuration data storage functionality with the logic circuit reconfiguration system. By merging the storage of optimized configuration data with the reconfiguration process, the system eliminates the need for separate, time-consuming optimization calculations during reconfiguration, thereby improving productivity while maintaining adaptability.
Data Source
AI summary
Disclosed is a semiconductor device which is intended to reduce the total number of storage element blocks that constitute a desired logic circuit. The semiconductor device includes N address lines (N is an integer equal to two or more), N data lines, and a plurality of storage sections. Each of the storage sections includes an address decoder for decoding an address supplied via the N address lines to output a word select signal to word lines; and a plurality of storage elements which are connected to the word lines and the data lines, each store data that constitute a truth table, and input or output the data via the data lines in accordance with the word select signal supplied via the word lines. The semiconductor device is adapted such that the N address lines for the storage sections are connected to the respective data lines of other N ones of the storage sections, while the N data lines for the storage sections are connected to the respective address lines of other N ones of the storage sections.