Shared Read/Write Line in Vertical 2T Memory Cells for Dense Arrays
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Solution Overview
Problem
Conventional volatile memory devices face challenges in reducing memory cell size to increase storage density due to physical limitations and fabrication constraints, leading to inefficiencies in storing and retrieving data.
Innovation Solution
The implementation of a 2T memory cell structure with a charge storage structure, where two transistors are stacked vertically, allowing for a smaller footprint and efficient data storage and retrieval through controlled voltage operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional memory cell structures are used to increase storage density, then the device area is reduced, but physical limitations and fabrication constraints prevent further shrinking
Solution Approach 1:
The patent transitions from planar memory cell layout to a vertical three-dimensional structure where bit lines extend in the Z-direction through multiple decks of memory cells. This dimensional change allows continued scaling of storage density without further reducing the planar footprint, overcoming fabrication constraints while maintaining manufacturability.
2Quantity of substance
If memory cell size is reduced to increase storage density, then device storage density increases, but data retention and access reliability deteriorate
Solution Approach 1:
By stacking multiple decks of memory cells vertically along the Z-axis, the patent achieves high storage density without compressing the lateral dimensions. Each memory cell maintains its full operational characteristics including charge storage capacity and transistor performance, ensuring data retention reliability is preserved while achieving increased storage density through vertical expansion.
Solution Approach 2:
The memory device is divided into multiple independent decks, each containing complete memory cells with charge storage structures. This segmentation allows each deck to operate independently with full data retention capabilities, preventing the reliability degradation that would result from further lateral miniaturization while achieving high density through vertical stacking.
3Ease of operation
If conventional access line structures are used, then read/write operations are simple, but access time increases due to longer signal paths
Solution Approach 1:
Bit lines are configured to extend vertically in the Z-direction through multiple decks of memory cells, enabling direct vertical access to all memory cells across different decks. This vertical routing eliminates the need for complex lateral signal routing and reduces the effective signal path length, thereby decreasing access time while maintaining operational simplicity through direct vertical addressing.
Data Source
AI summary
Some embodiments include apparatuses and methods operating the apparatuses. One of the apparatuses includes a first data line located over a substrate, a second data line located over the first data line, a third data line located over the second data line and electrically separated from the first and second data lines, and a memory cell coupled to the first, second, and third data lines. The memory cell includes a first material between the first and second data lines and electrically coupled to the first and second data lines; a second material located over the first data line and the first material, the second material electrically separated from the first material and electrically coupled to the third data line; and a memory element electrically coupled to the second material and electrically separated from the first material and first and second data lines.