Memory Compare Circuitry for Fast Glitchless Tag Matching
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Solution Overview
Problem
Existing compare circuitry in memory systems suffer from inefficiencies in performance, pipeline latency, and power consumption due to glitches and suboptimal design, particularly in applications like tag memory lookups.
Innovation Solution
Incorporating a novel compare circuitry design that utilizes selection logic and XNOR gates to perform comparisons only when a sense amplifier enable signal is active, minimizing glitches and optimizing speed and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If compare circuitry is integrated into memory, then comparison speed is improved and power consumption is reduced, but circuit complexity increases
Solution Approach 1:
The patent merges the compare circuitry with the memory structure by integrating the XNOR gate and selection logic directly into the memory array architecture. This allows the comparison operation to be performed concurrently with memory read operations, eliminating the need for separate comparison circuits and reducing overall system complexity while improving comparison speed.
Solution Approach 2:
The memory array is designed to serve multiple functions: storage, read operations, and comparison operations. The same memory structure performs both data storage and tag comparison, making the system more versatile and reducing the need for dedicated comparison hardware, thus lowering overall circuit complexity.
2Loss of time
If comparison output is generated continuously, then response time is reduced, but power consumption increases due to glitching
Solution Approach 1:
The selection logic enables the comparison output to be generated periodically rather than continuously. The output is only active during the memory read operation period when the sense amplifier is enabled, and remains inactive during other periods. This periodic operation reduces power consumption by minimizing glitching while maintaining fast response time during the active comparison window.
Data Source
AI summary
A compare circuitry that can be implemented in a memory circuit includes: selection logic coupled to a sense amplifier of the memory circuit, the selection logic structured to receive a sense amplifier enable signal, a column output from the sense amplifier, and a column output bar from the sense amplifier, wherein the selection logic is structured to pass through the column output and the column output bar when the sense amplifier enable signal is active and hold the column output and the column output bar at a same value when the sense amplifier enable signal is inactive; and an XNOR gate structured to receive the column output and the column output bar passed through the selection logic, a data input, and a data input bar and output a bit compare output.