Stacked Oxide Memory Cell Structure for Higher Storage Density
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving high storage capacity per unit area and efficient memory cell stacking with conventional structures, which limits their productivity and integration density.
Innovation Solution
A semiconductor device design featuring a memory cell structure with specific layers and conductors, insulators, and oxides, including In, Al, Ga, Y, Zn, and Sn elements, allowing for the creation of a novel stacked configuration with low resistance regions and high productivity, enabling increased storage capacity and efficient data handling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional memory cell structures are used, then device complexity is reduced, but storage capacity per unit area cannot be increased
Solution Approach 1:
The patent implements a three-dimensional stacked memory cell structure where multiple memory cells are vertically arranged along the channel length direction. This vertical stacking approach transitions from conventional two-dimensional planar layouts to three-dimensional architecture, enabling increased storage capacity per unit area by utilizing the vertical dimension for additional memory cell layers while maintaining manageable device complexity through systematic structural design
2Quantity of substance
If more memory cells are stacked to increase storage capacity, then productivity decreases due to manufacturing complexity
Solution Approach 1:
The patent divides the memory device into multiple discrete memory cell strings stacked vertically, with each string containing multiple memory cells sharing common bit lines and word lines. This segmentation allows for modular manufacturing where identical structural units can be replicated and stacked, improving productivity by enabling standardized fabrication processes while achieving high storage capacity through the multiplied individual cell units
Solution Approach 2:
The patent employs universal bit lines and word lines that serve multiple memory cells across different stacked layers. These common conductors are shared by multiple memory cell strings, reducing the total number of required interconnects and simplifying the manufacturing process. This multi-functional approach maintains high storage capacity while improving productivity by reducing fabrication steps and material requirements
3Reliability
If oxide semiconductor layers are used with specific resistance characteristics, then data retention improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent implements distinct oxide semiconductor layers with different resistance characteristics positioned at specific locations within the memory cell structure. The first oxide layer exhibits higher resistance for effective charge storage and data retention, while the second oxide layer exhibits lower resistance for efficient charge transport. This local differentiation of material properties achieves superior data retention while managing manufacturing precision requirements through clearly defined functional zones with standardized fabrication parameters for each layer type
Data Source
AI summary
A semiconductor device with a large storage capacity per unit area is provided.A semiconductor device includes a memory cell. The memory cell includes a first conductor; a first insulator over the first conductor; a first oxide over the first insulator and including a first region, a second region, and a third region positioned between the first region and the second region; a second insulator over the first oxide; a second conductor over the second insulator; a third insulator positioned in contact with a side surface of the first region; and a second oxide positioned on the side surface of the first region, with the third insulator therebetween. The first region includes a region overlapping the first conductor. The third region includes a region overlapped by the second conductor. The first region and the second region have a lower resistance than the third region.