Vertical Oxide Semiconductor Memory Cell for High-Density Data Retention
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving high storage capacity per unit area and efficient data retention due to limitations in transistor design and memory cell stacking.
Innovation Solution
A semiconductor device is designed with a novel structure comprising multiple transistors and capacitors arranged in a specific configuration, utilizing metal oxide semiconductors with extremely low off-state current, allowing for efficient data retention and high storage capacity through vertical transistor architecture and multi-level data storage techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are stacked vertically to increase storage capacity per unit area, then storage capacity per unit area is improved, but device structure complexity increases
Solution Approach 1:
The patent transitions from planar memory cell arrangement to vertical stacking architecture, utilizing the third dimension (height) to increase storage capacity. Multiple memory cells are stacked vertically with shared transistor structures, transforming the two-dimensional layout into a three-dimensional configuration that achieves higher density without proportionally increasing structural complexity
Solution Approach 2:
The patent implements shared transistor structures that serve multiple memory cells simultaneously. A single transistor structure can function as the access transistor for multiple stacked memory cells, reducing the total number of transistors required and simplifying the overall device structure while maintaining high storage capacity
2Ease of manufacture
If conventional transistors are used in stacked memory cells, then manufacturing is easier, but data retention is insufficient requiring frequent refresh operations
Solution Approach 1:
The patent changes the material parameter of the transistor from conventional silicon-based semiconductors to oxide semiconductor materials. This material substitution fundamentally alters the electrical characteristics, achieving extremely low off-state current levels that enable long-term data retention without refresh operations, while maintaining compatibility with existing semiconductor manufacturing processes
3Reliability
If oxide semiconductor transistors are used to achieve low off-state current, then data retention is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs atomic layer deposition (ALD) technology for oxide semiconductor layer formation, which provides self-limiting reaction characteristics that automatically ensure uniform thickness and composition. The ALD process inherently compensates for variations in precursor delivery and reaction conditions, achieving high manufacturing precision through self-regulating chemistry rather than relying on external control mechanisms
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables a semiconductor device with enhanced storage capacity per unit area and long-term data retention without the need for frequent refresh operations, reducing power consumption and improving reliability.
Implementation Method 1
a semiconductor device that can function by utilizing semiconductor characteristics
Data Source
AI summary
A semiconductor device with a large storage capacity per unit area can be provided. A memory cell including a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor, and a second capacitor includes a stack including a first conductor, a first insulator over the first conductor, a second conductor over the first insulator, a second insulator over the second conductor, and a third conductor over the second insulator; a first oxide arranged in a ring-like shape on a side surface of an opening portion of the second conductor; a fourth conductor arranged in a ring-like shape in contact with an inner wall of the first oxide; a cylindrical third insulator arranged to penetrate the stack, the first oxide, and the fourth conductor; and a second oxide arranged in contact with an inner wall of the third insulator.