DRAM Module Control Circuit for Selective Bank Activation
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Solution Overview
Problem
Conventional semiconductor modules consume unnecessary current as all DRAMs operate simultaneously, even when not all are needed, due to the lack of individual or group control over DRAM operations.
Innovation Solution
A module control circuit that includes an input unit, latch unit, comparator, and multiplexer to selectively generate and output command signals for DRAMs based on identification signals, allowing for individual or group operation of DRAMs, thereby reducing unnecessary current consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If all DRAMs are operated simultaneously according to conventional module design, then the module can perform high integration and high operating speed, but unnecessary current consumption occurs when not all DRAMs are needed
Solution Approach 1:
The patent divides the DRAM array into multiple banks (first bank, second bank, third bank, fourth bank) that can be independently controlled. Each bank has its own set of word lines and bit lines, allowing selective activation. The command decoder generates bank-specific control signals (e.g., /BA0, /BA1, /BA2, /BA3) to enable or disable individual banks based on the command received, thus segmenting the previously monolithic DRAM operation into controllable units that consume power only when needed.
Solution Approach 2:
The patent implements dynamic control of DRAM banks through a command decoder that interprets command signals and generates dynamic control signals for selective bank activation. The system transitions from static all-or-nothing bank activation to dynamic selective activation based on operational requirements. Control signals such as /BA0, /BA1, /BA2, and /BA3 are dynamically adjusted to activate only the necessary banks for each operation, enabling adaptive power management while maintaining high-speed performance when needed.
2Device complexity
If a command decoder generates a single input command for all DRAMs, then the module structure is simple, but individual or group control of DRAMs is not possible
Solution Approach 1:
The command decoder is segmented into multiple functional units that process commands differently for different banks. Instead of a single monolithic decoder, the patent employs multiple decode paths that can independently control different bank groups. This segmentation allows the same physical decoder structure to provide differentiated control signals for various bank combinations, achieving both structural simplicity and control flexibility.
Solution Approach 2:
The command decoder is designed with multi-functionality to handle various command types (activate, read, write, refresh, power-down) and route them to appropriate banks. The decoder structure can interpret a single command signal and generate multiple bank control signals simultaneously, enabling one decoder to perform multiple control functions. This universal design allows the decoder to adapt to different operational modes and bank configurations without requiring separate dedicated decoders for each bank.
Data Source
AI summary
A module control circuit includes an input unit configured to receive a plurality of data signals from a plurality of data input/output pins and output an identification signal and an internal command signal. A latch unit is configured to latch the identification signal in accordance with a first enable signal to output a first group identification signal, latch the identification signal in accordance with a second enable signal to output a second group identification signal, and latch the internal command signal in accordance with the second enable signal to output a group command signal. A comparator is configured to compare the first group identification signal with the second group identification signal, and generate a selection signal. A multiplexer is configured to select one of the group command signal and a module command signal as an input command in response to the selection signal.