Separate Memory Supply Voltage for Low-Power Logic Circuits
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Solution Overview
Problem
Integrated circuits with memory, such as SRAM, face challenges in reducing power consumption while maintaining memory robustness, as lowering the supply voltage below a certain threshold impairs memory reliability due to changes in transistor resistances and high threshold voltage transistors, making it difficult to achieve efficient power management.
Innovation Solution
The solution involves separating the supply voltage for logic circuits and memory circuits, allowing the logic circuits to operate at a lower voltage while maintaining the memory circuits at a minimum voltage that ensures robust memory operation, using a level shifter and word line drivers supplied by the higher voltage to ensure reliable read/write access, and employing clock gating and level shifting to manage signals across voltage domains.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the supply voltage is reduced to decrease power consumption, then power consumption is reduced, but memory robustness deteriorates due to changes in transistor resistances and high threshold voltage transistors
Solution Approach 1:
The integrated circuit is divided into two separate voltage domains: a first voltage domain for logic circuits operating at a lower voltage (first supply voltage) and a second voltage domain for memory circuits operating at a higher voltage (second supply voltage). This segmentation allows each domain to operate at its optimal voltage level, reducing overall power consumption while maintaining memory robustness.
Solution Approach 2:
Different voltage levels are applied to different parts of the circuit based on their specific requirements. Logic circuits receive a lower voltage to minimize power consumption, while memory circuits receive a higher voltage to ensure reliable operation. This local differentiation of voltage quality resolves the contradiction between power efficiency and reliability.
2Use of energy by moving object
If the supply voltage is reduced below a certain threshold, then power consumption is reduced, but the ability to reliably read and write memory decreases
Solution Approach 1:
The circuit is segmented into logic and memory portions with separate voltage supplies. The memory portion operates at a higher voltage threshold that ensures reliable read/write operations, while the logic portion operates at a lower voltage to reduce power consumption. This segmentation eliminates the need to compromise memory reliability for overall power reduction.
Solution Approach 2:
The voltage parameter is changed differently for different circuit portions. By providing a second supply voltage to the memory circuit that is higher than the first supply voltage to the logic circuit, the patent changes the operating parameters locally to maintain memory reliability while reducing overall power consumption.
3Use of energy by moving object
If separate supply voltages are used for logic and memory circuits, then power consumption is reduced and memory robustness is maintained, but device complexity increases due to additional voltage domains and level shifting requirements
Solution Approach 1:
Level shifters are introduced as intermediary circuits to bridge the two voltage domains. These level shifters translate signals between the first voltage domain (logic) and the second voltage domain (memory), enabling communication between the different voltage domains without requiring complex direct interfacing. This intermediary approach manages the complexity of multi-voltage operation.
Solution Approach 2:
The level shifter circuits perform multiple functions: they translate voltage levels between domains, enable signal communication across voltage boundaries, and help manage the interaction between logic and memory circuits. This multi-functionality reduces the need for separate dedicated circuits for each task.
Data Source
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AI summary
In one embodiment, an integrated circuit comprises at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and written responsive to the logic circuit even if the first supply voltage is less than the second supply voltage during use. In another embodiment, a method comprises a logic circuit reading a memory cell, the logic circuit supplied by a first supply voltage; and the memory cell responding to the read using signals that are referenced to the first supply voltage, wherein the memory cell is supplied with a second supply voltage that is greater than the first supply voltage during use.