Dynamic Logic Pull-Up Timing to Prevent Evaluation Contention
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Solution Overview
Problem
Dynamic logic circuits face contention issues between pull-up and pull-down circuits during the evaluation phase, leading to potential erroneous operations due to unbalanced drive strengths and leakage currents, especially when multiple evaluation circuits share a common dynamic node.
Innovation Solution
Incorporating a programmable delay unit that activates a second pull-up transistor after a predetermined delay time subsequent to the start of the evaluation phase, creating a pull-up path to prevent contention and counteract leakage currents, thereby ensuring accurate logic evaluation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single pull-up transistor is used during the precharge phase, then the dynamic node can be efficiently precharged to logic high, but contention occurs during the evaluation phase when the pull-up and pull-down circuits are simultaneously active
Solution Approach 1:
The pull-up circuit is segmented into two transistors (first pull-up transistor for precharge phase and second pull-up transistor for evaluation phase) that operate at different times. This temporal segmentation eliminates simultaneous activation of pull-up and pull-down circuits, preventing contention while maintaining reliable logic evaluation.
2Reliability
If the second pull-up transistor is activated immediately at the start of the evaluation phase, then leakage currents are counteracted, but contention with the pull-down circuit occurs due to unbalanced drive strengths
Solution Approach 1:
The first pull-up transistor performs preliminary action by precharging the dynamic node to logic high before the evaluation phase begins. This preliminary charging ensures the node is properly initialized, and when the second pull-up transistor activates later, it only needs to maintain the logic level against leakage, not compete with the pull-down circuit.
Solution Approach 2:
The pull-up circuit operates periodically with the first pull-up transistor active during the precharge phase and the second pull-up transistor active during the evaluation phase. This periodic activation pattern synchronized with the clock signal prevents overlap between pull-up and pull-down operations, eliminating contention.
3Reliability
If the first pull-up transistor remains active during the evaluation phase, then the dynamic node is held high, but leakage currents cause erroneous logic evaluation
Solution Approach 1:
The pull-up circuit dynamically switches from the first pull-up transistor during precharge to the second pull-up transistor during evaluation. This dynamic reconfiguration allows the circuit to adapt to different operational phases, enabling the second transistor to counteract leakage currents during evaluation while the first transistor handles precharging, optimizing performance for each phase.
Data Source
AI summary
A circuit including is disclosed. The circuit includes a precharge circuit configured to pull a dynamic node toward a voltage present on the voltage supply node during a precharge phase, and an evaluation circuit configured to, during an evaluation phase, pull the dynamic node toward a ground voltage responsive to a first input condition and configured to inhibit pulling of the dynamic node down responsive to a second input condition. A pull-up circuit coupled between the first dynamic node and the voltage supply node includes first and second pull-up transistors. The first pull-up transistor is configured to activate responsive to the precharge phase. The second pull-up transistor is configured to activate at a delay time subsequent to entry of the evaluation phase. When the first and second pull-up transistors are active, a pull-up path is provided between the dynamic node and the voltage supply node.