SRAM Redundancy Memory Power Gating for FRAM Arrays
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Solution Overview
Problem
The power consumption of redundancy circuits in solid-state memory systems, particularly in implantable medical devices, is high due to the use of static random access memory (SRAM) for storing addresses and enable bits, which consumes power even when redundancy is not enabled, and is vulnerable to soft-error failures.
Innovation Solution
The implementation of a redundancy circuit with SRAM that gates power to data word cells based on enable bits, using majority encoding to enable all redundant elements for a segment, reducing power consumption and vulnerability to soft-error failures by selectively powering only necessary memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If redundancy circuits are implemented to replace defective memory cells, then reliability is improved, but power consumption increases
Solution Approach 1:
The patent implements dynamic power gating for redundancy circuits. The redundancy search and replacement operations are performed only when needed (when defective cells are detected), rather than continuously. Power is supplied to redundancy circuits conditionally based on operational requirements, reducing overall power consumption while maintaining reliability benefits.
Solution Approach 2:
The patent applies power gating selectively to specific redundancy circuit components rather than the entire memory system. Individual redundancy circuits or blocks can be powered down when not needed, allowing localized power management that reduces total power consumption while maintaining reliability where active redundancy is provided.
2Reliability
If more redundant memory elements are provided, then reliability is improved, but device area increases
Solution Approach 1:
The patent divides the memory array into multiple segments or blocks, each with its own redundancy circuits. This segmentation allows redundancy to be provided locally where needed rather than requiring global redundancy for the entire memory array, reducing the overall area overhead while maintaining reliability across the full memory capacity.
Solution Approach 2:
The patent implements partial redundancy where not every memory block requires full redundancy resources. Some blocks may have redundancy while others rely on error correction codes or other protection mechanisms, providing adequate reliability with reduced total redundancy area compared to full redundancy across all blocks.
3Area of stationary object
If minimum size transistor gates are used for memory cells, then area is reduced, but manufacturing yield decreases
Solution Approach 1:
The patent incorporates redundancy circuits and defect mapping capabilities during manufacturing. Defective cells are identified through testing, and their locations are stored in defect maps. Redundancy circuits are pre-configured to replace defective cells, cushioning against manufacturing defects and ensuring high yield despite using minimum-size transistors that are more susceptible to manufacturing variations.
Data Source
AI summary
A static RAM redundancy memory for use in combination with a non-volatile memory array, such as ferroelectric RAM (FRAM), in which the power consumption of the SRAM redundancy memory is reduced. Each word of the redundancy memory includes data bit cells for storing addresses of memory cells in the FRAM array to be replaced by redundant elements, and also enable bits indicating whether redundancy is enabled for those addresses. A logical combination of the enable bits in a given word determines whether the data bit cells in that word are powered-up. As a result, the power consumption of the redundancy memory is reduced to the extent that redundancy is not enabled for segments of the FRAM array.