FeFET Synapse Circuit for In-Memory Euclidean Distance Calculation

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Solution Overview

Problem

The slow training process of neural networks due to the need for extensive memory access and computations in updating millions of weight values in machine learning algorithms, particularly in deep neural networks, necessitates a hardware acceleration solution for Euclidean distance calculations.

Innovation Solution

The use of reconfigurable ferroelectric field-effect transistors (FeFETs) to represent nodes in a Self-Organizing Feature Map (SOFM), where the weights are stored as threshold voltages and updated without memory access, utilizing the saturation drain current to determine and compute Euclidean errors directly.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If conventional software-based neural network training is used, then weight updates can be performed with standard computing resources, but the training process becomes extremely slow due to frequent memory access and extensive computations

Engineering Contradiction:
Improvetraining speedVSAvoidtraining time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent replaces conventional software-based computation with hardware-based computation using field-effect transistors. The FETs physically embody the neural network weights through their threshold voltages, and Euclidean distance calculations are performed through physical current measurements rather than software algorithms. This hardware substitution eliminates the bottleneck of memory access and software computation, dramatically accelerating training speed.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The FET-based synapses perform computations autonomously using their inherent physical properties. The threshold voltage of each FET directly represents a weight, and the saturation drain current automatically provides the squared Euclidean distance calculation when an input voltage is applied. This self-service mechanism eliminates the need for external memory access and complex computational logic, enabling parallel processing of all synapses simultaneously.

Inventive Principle:
Principle #25Self-service

2Quantity of substance

If millions of weight values are stored in memory for neural network training, then complete neural network models can be maintained, but memory access becomes a bottleneck that slows down the training process

Engineering Contradiction:
Improvenumber of weight valuesVSAvoidweight update speed
Core Design Contradiction:
Quantity of substanceVSSpeed

Solution Approach 1:

The patent merges the weight storage function and the computation function into a single FET device. The threshold voltage of each FET serves dual purposes: it stores the weight value and simultaneously enables Euclidean distance calculation through current measurement. This merging eliminates the separate memory structure that would require access operations, allowing instant weight retrieval and computation through physical measurement.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent extracts the weight values from conventional memory structures and embeds them directly into the physical properties of FET devices. By storing weights as threshold voltages within the transistors themselves rather than in external memory, the system eliminates the memory access bottleneck while maintaining the ability to represent millions of weight values through the electrical characteristics of the FET array.

Inventive Principle:
Principle #2Taking out (Extraction)

3Measurement precision

If extensive computations are performed for each weight update in neural network training, then accurate gradient calculations can be achieved, but the computational overhead significantly increases training time

Engineering Contradiction:
ImproveEuclidean distance accuracyVSAvoidcomputational complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent replaces complex software-based Euclidean distance calculations with a simple physical measurement process. Instead of computing the squared differences and summing them through software algorithms, the system applies an input voltage equal to the input attribute to the FET and directly measures the saturation drain current, which physically represents the squared Euclidean distance. This substitution maintains measurement precision while dramatically reducing computational complexity.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach significantly accelerates the training process by eliminating the need for memory access and reducing computational overhead, allowing for faster training of neural networks.

Implementation Method 1

reconfigurable ferroelectric field-effect transistors (FeFETs) to represent nodes in a Self-Organizing Feature Map (SOFM), where the weights are stored as threshold voltages

Methodology Applied
Scientific EffectFerroelectric effect:

Implementation Method 2

a first transistor channel of the first FeFET synapse and a second transistor channel of the second FeFET synapse are connected in parallel between a source and a drain

Methodology Applied
Scientific EffectElectrical conduction: Conduction (electrical)

Implementation Method 3

a current sensor measures a saturation drain current of the first reconfigurable field-effect transistor and the second reconfigurable field-effect transistor and determines a Euclidean error based on the saturation drain current

Methodology Applied
Scientific EffectSaturation current measurement:

Data Source

PatentUS20240194237A1Ferroelectric field effect transistors based approach for euclidean distance calculation in neuromorphic hardware
Publication Date: 2024.06.13 UNIVERSITY OF CINCINNATI
  • US20240194237A1 patent drawing
  • US20240194237A1 patent drawing
  • US20240194237A1 patent drawing

AI summary

An apparatus may comprise a synapse comprising a first reconfigurable field-effect transistor; a second reconfigurable field-effect transistor connected in parallel to the first reconfigurable field-effect transistor; an input voltage applied to each of the first reconfigurable field-effect transistor and the second reconfigurable field-effect transistor corresponding to an input attribute associated with an error computation; and a current sensor measures a saturation drain current of the first reconfigurable field-effect transistor and the second reconfigurable field-effect transistor and determines a Euclidean error based on the saturation drain current of the FETs