Series STT-SOT MRAM Stack for Four-State AI Weight Storage
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Solution Overview
Problem
Current magnetic random access memory (MRAM) technologies, including both spin-transfer torque (STT)-MRAM and spin-orbit torque (SOT)-MRAM, face challenges in achieving multiple resistance states necessary for accurate weight storage in artificial intelligence (AI) chips, particularly for deep neural networks, as they typically operate in binary states which are insufficient for preserving accuracy and are power-intensive.
Innovation Solution
The integration of a spin-transfer torque (STT) MRAM stack with a spin-orbit torque (SOT) MRAM stack in series, utilizing a heavy metal rail to flip the SOT free-layer magnetic orientation in response to horizontal signals, enabling four distinct resistance states (00, 01, 10, 11) for efficient weight storage, thereby reducing power consumption and hardware requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If binary state operation is used in MRAM, then device complexity is reduced, but measurement precision and information storage accuracy are insufficient for AI weight storage
Solution Approach 1:
The patent segments the memory system into two independent MRAM stacks (first and second stacks) with different torque mechanisms. Each stack can independently represent binary states, and their combination enables four distinct resistance states (00, 01, 10, 11), providing sufficient precision for weight storage while maintaining simple binary operations within each stack.
Solution Approach 2:
The patent employs a composite memory structure combining two different MRAM technologies (STT-MRAM and SOT-MRAM) in series. This composite approach leverages the strengths of both technologies to achieve multi-state operation, where the combination of two binary stacks creates four distinguishable resistance states for accurate weight representation.
2Measurement precision
If multiple resistance states are achieved through stacking MRAM stacks, then weight storage accuracy is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent divides the complex multi-state memory into two separate, independently fabricable MRAM stacks. Each stack is designed and fabricated using established processes, then combined in series. This segmentation reduces manufacturing complexity compared to creating a single complex multi-state cell, as each stack can be optimized and tested independently before integration.
3Loss of energy
If STT-MRAM is used for weight storage, then non-volatile memory with low leakage power is achieved, but current consumption during write operations is high
Solution Approach 1:
The patent segments the write operation into two independent paths: one through the STT-MRAM stack and another through the SOT-MRAM stack. This allows the system to leverage the low leakage power of STT-MRAM while using SOT-MRAM's more efficient write mechanism, reducing the overall energy required for write operations while maintaining non-volatile storage characteristics.
4Use of energy by moving object
If SOT-MRAM with heavy metal rail is used, then write energy efficiency is improved, but manufacturing process complexity increases
Solution Approach 1:
The patent segments the memory device into modular stacks that can be fabricated using separate process flows. The heavy metal rail structure in the SOT-MRAM stack is designed as an integrated component that can be deposited and patterned using standard semiconductor manufacturing techniques, reducing overall manufacturing complexity despite the advanced write mechanism.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for accurate AI chip inference with no loss in prediction accuracy, achieving area and power savings by enabling low-power SOT-MRAM switching and reduced bit usage, resulting in a more compact and efficient memory circuit.
Implementation Method 1
Spin-orbit torque (SOT) MRAM separates the read and write path of the memory. SOT-MRAM devices feature a switching of the free magnetic layer done by injecting an in-plane current in an adjacent SOT layer
Implementation Method 2
Spin-transfer torque MRAM (STT-MRAM) is a non-volatile memory with near-zero leakage power consumption which is a major advantage over charge-based memories such as static RAM (SRAM) and dynamic RAM (DRAM). STT-MRAM is a two-terminal device that uses spin-aligned (e.g., polarized) electrons to directly torque the domains
Implementation Method 3
MRAM is a type of non-volatile random-access memory (RAM) which stores data in magnetic domains. Unlike conventional RAM technologies, data in MRAM is not stored as electric charge or current flows, but by magnetic storage elements formed from two ferromagnetic plates, each of which can hold a magnetization, separate by a thin insulating layer
Data Source
AI summary
Embodiments disclosed herein include a semiconductor structure. The semiconductor structure may include a spin transfer torque (STT) magnetoresistive random access memory (MRAM) stack. The semiconductor structure may also include a spin orbit torque (SOT) MRAM stack vertically in series with the STT-MRAM. The SOT-MRAM stack may include a heavy metal spin hall effect rail configured to flip an SOT free-layer magnetic orientation in response to a horizontal signal through the heavy metal rail.