3D Cross-Point Memory Array Fabrication With Via-Patterned Deck Stacking
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Solution Overview
Problem
Current methods for fabricating three-dimensional (3D) memory devices face challenges in increasing memory cell density and reducing fabrication costs, as they require repetitive processing steps that increase costs due to the need for multiple photomasking and other processing steps.
Innovation Solution
The techniques involve forming a 3D cross-point memory array by creating a composite stack with intersecting access lines, where vias are used to selectively remove and replace material, allowing for concurrent formation of multiple decks of memory cells with reduced processing steps, thereby minimizing fabrication costs and enhancing memory cell density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional fabrication techniques are used to build 3D memory arrays, then memory capacity can be increased, but the number of processing steps increases significantly
Solution Approach 1:
The fabrication process is segmented into distinct decks (first deck, second deck, etc.), where each deck is formed independently and then stacked. This allows complex 3D memory structures to be built by repeating standardized deck formation steps rather than creating the entire structure in one complex process.
Solution Approach 2:
The patent transitions from planar 2D memory fabrication to 3D vertical stacking by forming memory cells in multiple decks stacked along the vertical direction. Multiple bit lines and word lines are arranged in different vertical layers, enabling increased storage capacity without proportionally increasing processing complexity.
2Quantity of substance
If more decks of memory cells are stacked to increase capacity, then memory density improves, but fabrication precision requirements increase
Solution Approach 1:
Socket regions are formed in advance during the fabrication of lower decks, creating predefined connection points before upper decks are stacked. This preliminary preparation ensures that when decks are stacked and connected, the alignment requirements are already satisfied by the pre-formed socket structures.
Solution Approach 2:
Socket regions act as intermediary connection structures between stacked decks. These sockets provide mechanical and electrical coupling interfaces that facilitate precise alignment and connection between bit lines and word lines across different vertical layers without requiring extremely tight tolerances.
3Adaptability or versatility
If complex socket regions are formed to enable 3D stacking, then device functionality improves, but fabrication complexity increases
Solution Approach 1:
The socket region formation is merged with the existing fabrication process steps for forming bit lines and interlayer dielectric layers. Rather than adding a separate complex socket fabrication process, the socket regions are created as an integrated part of the standard memory cell formation steps, combining multiple functions into a unified process sequence.
Data Source
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AI summary
Methods and apparatuses for a cross-point memory array and related fabrication techniques are described. The fabrication techniques described herein may facilitate concurrently building two or more decks of memory cells disposed in a cross-point architecture. Each deck of memory cells may include a plurality of first access lines (e.g., word lines), a plurality of second access lines (e.g., bit lines), and a memory component at each topological intersection of a first access line and a second access line. The fabrication technique may use a pattern of vias formed at a top layer of a composite stack, which may facilitate building a 3D memory array within the composite stack while using a reduced number of processing steps. The fabrication techniques may also be suitable for forming a socket region where the 3D memory array may be coupled with other components of a memory device.