3D Stacked Word Line Layout for Higher-Density Memory Arrays
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Solution Overview
Problem
Two-dimensional semiconductor devices face limitations in integration due to the high cost of fine pattern forming technology, hindering cost-effective increases in integration density.
Innovation Solution
A three-dimensional semiconductor memory device with a staircase structure of alternating word lines and interlayer insulating patterns, featuring sub-gate electrodes and a cell array structure that allows for increased integration density and improved reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional or planar semiconductor devices are used, then manufacturing process is simpler, but integration density cannot be increased sufficiently
Solution Approach 1:
The patent transitions from two-dimensional planar structures to three-dimensional stacked structures by vertically stacking multiple memory cell layers. Each layer includes channel patterns, bit lines, and word lines arranged in three dimensions, enabling increased integration density without being constrained by planar area limitations. The stack structure extends in the vertical direction (third direction) perpendicular to the substrate plane,实现ing spatial utilization in multiple dimensions.
2Quantity of substance
If advanced pattern forming technology is used to increase integration, then integration density improves, but manufacturing cost increases significantly
Solution Approach 1:
The memory device is divided into multiple discrete memory cell layers stacked vertically, with each layer containing complete sets of channel patterns, bit lines, and word lines. This segmentation allows each layer to be formed using standard semiconductor manufacturing processes without requiring extremely advanced pattern forming technology, thereby controlling manufacturing costs while achieving high integration through vertical stacking.
Solution Approach 2:
By moving from two-dimensional planar integration to three-dimensional vertical integration, the patent achieves increased storage capacity without proportionally increasing manufacturing complexity. The vertical stacking approach uses conventional fabrication processes repeated across multiple layers, avoiding the need for expensive cutting-edge lithography that would be required for planar scaling.
3Quantity of substance
If three-dimensional stacked structure is implemented, then integration density increases, but interconnection complexity with peripheral circuits increases
Solution Approach 1:
Word line pads are formed in advance in the peripheral circuit region before final interconnections are established. These pads serve as pre-positioned connection points that simplify the subsequent bonding process with peripheral circuits. The preliminary formation of these pads in the third mold structure enables easier interconnection without adding significant complexity to the overall system.
Solution Approach 2:
The patent introduces intermediate connection structures including word line pads and cell contact plugs that act as mediators between the three-dimensional memory cell arrays and peripheral circuits. These intermediate elements provide standardized interfaces that simplify the bonding process, allowing modular integration without directly connecting every memory element to peripheral circuits, thereby managing interconnection complexity.
Data Source
AI summary
A semiconductor memory device may include a lower layer including a first region and a second region, the lower layer extending in a first direction and a second direction perpendicular to the first direction, and a stack including word lines and interlayer insulating patterns, which are alternatingly stacked in a third direction perpendicular to the first direction and the second direction, the stack having a staircase structure on the second region. The word lines may extend from the first region to the second region in the first direction. Each of the word lines may include sub-gate electrodes, which extend parallel to each other in the first region, and a word line pad, which is connected in common to the sub-gate electrodes in the second region.