3D Cross-Point Memory Array Fabrication with Shared Via Patterning
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Solution Overview
Problem
Current memory device fabrication techniques face challenges in increasing memory cell density and reducing manufacturing costs, particularly due to the need for repeated processing steps and photomasking, which can offset the benefits of three-dimensional integration.
Innovation Solution
The method involves forming a three-dimensional cross-point memory array by concurrently building multiple decks of memory cells using a pattern of vias at the top layer of a composite stack, selectively removing and replacing material to form electrodes and memory cells, and reducing the number of processing steps, such as photomasking, to facilitate the construction of a 3D memory device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple decks of memory cells are formed using conventional fabrication techniques, then memory cell density increases, but the number of processing steps and photomasking operations increases
Solution Approach 1:
The patent combines the formation of multiple decks of memory cells into a single integrated fabrication process. By using a common via pattern formed through the top layer to define features across multiple decks simultaneously, the method merges what would traditionally require separate processing sequences into one unified operation, thereby increasing memory cell density without proportionally increasing processing step complexity
Solution Approach 2:
The via pattern formed at the top layer serves multiple functions: it defines the geometry for electrodes in one deck, defines the geometry for memory cells in another deck, and provides alignment references for subsequent processing steps. This multi-functional use of a single patterned structure eliminates the need for separate photomasking operations for each deck, resolving the contradiction between increased density and reduced processing complexity
2Quantity of substance
If conventional fabrication techniques are used to form multiple decks, then memory capacity increases, but fabrication costs increase due to repeated photomasking
Solution Approach 1:
The patent merges multiple photomasking operations into a single photomasking step by using a common via pattern that serves all decks. This consolidation reduces the number of expensive photomasking cycles required, thereby increasing memory capacity without proportionally increasing fabrication costs
Solution Approach 2:
The method uses the same via pattern design and material stack configuration across multiple decks, allowing the fabrication process to be replicated vertically without requiring new pattern designs or additional photomasking for each deck. This copying approach enables cost-effective scaling of memory capacity
3Quantity of substance
If three-dimensional integration is implemented, then areal density increases, but processing complexity increases due to repeated processing steps
Solution Approach 1:
The patent resolves processing complexity by moving the pattern definition to the top surface dimension rather than requiring sequential patterning through each layer. The via pattern formed at the top layer projects downward to define features in multiple decks, using the vertical dimension for integration while maintaining simplicity in the horizontal patterning dimension
Solution Approach 2:
The method performs the critical patterning action preliminarily by forming the via pattern through the top layer before subsequent processing steps. This preliminary pattern definition serves as a template for all downstream operations, eliminating the need for repeated patterning steps and reducing overall processing complexity while enabling three-dimensional integration
Data Source
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AI summary
Methods and apparatuses for a cross-point memory array and related fabrication techniques are described. The fabrication techniques described herein may facilitate concurrently building two or more decks of memory cells disposed in a cross-point architecture. Each deck of memory cells may include a plurality of first access lines (e.g., word lines), a plurality of second access lines (e.g., bit lines), and a memory component at each topological intersection of a first access line and a second access line. The fabrication technique may use a pattern of vias formed at a top layer of a composite stack, which may facilitate building a 3D memory array within the composite stack while using a reduced number of processing steps. The fabrication techniques may also be suitable for forming a socket region where the 3D memory array may be coupled with other components of a memory device.