Vertical 2T Memory Cell Layout With Shields for Read Margin
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional volatile memory devices face challenges in reducing capacitive coupling between adjacent memory cells, leading to increased size and power dissipation, which hinders the achievement of higher storage density and efficient operation.
Innovation Solution
The implementation of a memory device with a 2T cell structure, utilizing a single access line and shield structures to reduce capacitive coupling, allowing for a smaller footprint and improved read signal margin, and employing a cross-point gain cell structure for efficient data access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional memory cell structures are used to increase storage density, then device storage density improves, but capacitive coupling between adjacent memory cells increases
Solution Approach 1:
A shield structure is introduced as an intermediary element positioned between adjacent memory cell charge storage structures. This shield acts as a mediator that blocks or reduces the capacitive coupling field lines between neighboring cells, thereby reducing harmful capacitive coupling while preserving the high-density layout. The shield is typically connected to a fixed potential (such as ground or a reference voltage) to effectively terminate electric field lines.
Solution Approach 2:
The patent converts the harmful effect of capacitive coupling into a beneficial shielding effect by strategically placing conductive shield structures. These shields, when biased at appropriate potentials, transform the problematic electric field interactions into controlled field termination, thereby reducing noise and interference between adjacent cells while maintaining compact cell geometry.
2Quantity of substance
If memory cell size is reduced to increase storage density, then device storage density improves, but fabrication constraints and physical limitations increase
Solution Approach 1:
The memory cell design transitions from a planar two-dimensional layout to a three-dimensional vertical structure. By stacking transistor gates and charge storage structures vertically, the patent achieves higher storage density without proportionally reducing the lateral footprint, thereby easing fabrication constraints while maintaining high density. The vertical arrangement allows for better separation of functional elements in the third dimension.
Solution Approach 2:
The patent employs a nested structure where multiple functional elements (transistors, gates, charge storage regions) are vertically stacked and interconnected in a compact arrangement. The shield structures are nested between these vertical elements, creating a space-efficient configuration that reduces lateral dimensions while maintaining functionality and reducing capacitive coupling.
3Measurement precision
If shield structures are added to reduce capacitive coupling, then read signal margin improves, but device complexity increases
Solution Approach 1:
The shield structures are designed to serve multiple functions simultaneously: they reduce capacitive coupling between adjacent cells, provide mechanical support, define cell boundaries, and can be integrated with existing word lines or bit lines. This multi-functionality reduces the need for additional separate structures, thereby limiting the increase in device complexity while achieving improved read signal margin.
Solution Approach 2:
The patent merges the shield structure with existing memory cell components such as word lines or bit lines, or integrates them into the same fabrication layers as transistors and capacitors. By combining the shielding function with structural or interconnect elements that already exist in the memory array, the patent reduces read signal interference without proportionally increasing device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables a more compact and power-efficient memory device with enhanced operational performance by minimizing capacitive coupling and utilizing a single access line for both read and write operations, thereby improving storage density and processing efficiency.
Implementation Method 1
The memory device described herein can include shield structures between charge storage structures of adjacent memory cells. The shield structures can reduce capacitive coupling between adjacent charge storage structures of adjacent memory cells.
Data Source
AI summary
Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a conductive region, a first data line, a second data line, a first memory cell coupled to the first data line and the conductive region, a second memory cell coupled to the second data line and the conductive region, a conductive structure, and a conductive line. The first memory cell includes a first transistor coupled to a second transistor, the first transistor including a first charge storage structure. The second memory cell includes a third transistor coupled to a fourth transistor, the third transistor including a second charge storage structure. The conductive structure is located between and electrically separated from the first and second charge storage structures. The conductive line forms a gate of each of the first, second, third, and fourth transistors.