Output Enable Timing Circuit for Consecutive Memory Reads
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional output enable signal generating circuits in semiconductor memory devices fail to activate the output enable signal at the desired time for consecutive read commands, especially when the second read command is input before the external clock count value is compared with the DLL clock count value, leading to malfunctioning and impaired precision and reliability, particularly as CAS latency increases with higher operating frequencies.
Innovation Solution
The proposed solution involves an output enable signal generating circuit with multiple latches and comparators that latch external clock signals for each read command, ensuring the output enable signal is activated at the appropriate time for each read command, using a first count value generated by an internal clock and a second count value by an external clock, with a comparison unit activating the signal when the two values match, thereby addressing the timing issues in domain crossing operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional output enable signal generating circuit is used, then the circuit structure is simple, but the output enable signal cannot be activated at the desired time for consecutive read commands, leading to malfunctioning
Solution Approach 1:
The patent divides the output enable signal generation into multiple independent paths, each handling a specific read command. Multiple latches (first latch, second latch) and comparators are used to process consecutive read commands separately, ensuring each command gets proper timing treatment rather than using a single shared generation path.
Solution Approach 2:
The patent uses latches to capture and hold the external clock count values at specific timing points before comparison. The first latch latches the external clock count value in response to the first read command, and the second latch latches in response to the second read command, preparing the values in advance for accurate comparison with DLL clock count values.
2Productivity
If the operating frequency is increased to improve productivity, then data processing speed increases, but CAS latency increases leading to timing errors in output enable signal generation
Solution Approach 1:
The patent uses multiple comparators to compare external clock count values with DLL clock count values at different timing points corresponding to different CAS latencies. The first comparator handles comparisons for first CAS latency, while the second comparator handles comparisons for second CAS latency, allowing the system to accommodate varying latency requirements at high operating frequencies.
3Measurement precision
If a single latch and comparator are used to reduce device complexity, then the circuit is simpler, but precision and reliability are impaired due to inability to handle consecutive read commands properly
Solution Approach 1:
The patent segments the timing comparison function into multiple independent comparator units. Each comparator is dedicated to comparing count values for a specific read command, ensuring that timing accuracy is maintained for each command independently without interference from other commands in the consecutive read sequence.
Data Source
AI summary
An output enable signal generating circuit including a first count value generation unit that provides a first count value by executing a counting operation, starting from an initial count value corresponding to a CAS latency information, the counting operation being executed in response to an internal clock signal, a second count value generation unit that provides a second count value that is counted in response to an external clock signal and an output enable signal generation unit for generating an output enable signal that is activated at every timing when the second count value and the first count value become equal to each other, in response to each of a plurality of read commands.