Ferroelectric Gate Stack Switching Element for Negative Capacitance Memory
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor memory devices face challenges in achieving high integration density and performance while maintaining low costs, particularly in the development of 3D semiconductor memory devices where improving operation speed and reliability is crucial.
Innovation Solution
The integration of a switching element with a negative capacitor structure, utilizing ferroelectric materials in the gate dielectric layers to achieve negative capacitance, which enhances the operation speed and reliability of semiconductor memory devices by allowing for precise control of capacitance and potential levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional gate dielectric structures are used in semiconductor memory devices, then the device structure is simple and easy to manufacture, but the operation speed and reliability are insufficient
Solution Approach 1:
The patent employs a composite gate dielectric structure consisting of a first gate dielectric layer (e.g., SiO2 or Si3N4) and a second gate dielectric layer containing ferroelectric material (e.g., HfO2, Pb(Zr,Ti)O3, or Pb1-xLaxZr1-yTiyO3). This composite structure combines the electrical insulation properties of conventional dielectrics with the negative capacitance effect of ferroelectric materials, thereby improving operation reliability and on/off response speed while managing the increased structural complexity through systematic layer integration.
Solution Approach 2:
The patent utilizes the phase transition properties of ferroelectric materials to achieve parameter changes in capacitance. By controlling the polarization state of the ferroelectric layer, the gate structure can exhibit negative capacitance, which enables sub-60mV/dec subthreshold swing and significantly improves switching speed. The thickness of the ferroelectric layer is specifically optimized (e.g., 5-50 nm) to maintain stable negative capacitance while ensuring reliable operation.
2Area of stationary object
If higher integration density is achieved through 3D structure, then the area occupied by memory cells is reduced, but the operation speed and reliability become more difficult to maintain
Solution Approach 1:
The patent transitions from planar 2D gate structures to three-dimensional stacked gate structures. Multiple gate dielectric layers and gate electrodes are stacked vertically to form multi-layer gate stacks, enabling higher integration density while maintaining effective gate control. The 3D stacking allows memory cells to be arranged in vertical columns, significantly reducing the area occupied per memory cell while preserving operation reliability through the negative capacitance effect in each stacked layer.
3Speed
If ferroelectric material is introduced to achieve negative capacitance, then the on/off response speed is improved, but the manufacturing process becomes more complex
Solution Approach 1:
The gate dielectric structure is segmented into multiple functional layers: a first gate dielectric layer providing electrical insulation and a second gate dielectric layer containing ferroelectric material responsible for negative capacitance. This segmentation allows each layer to be optimized independently for its specific function, improving on/off response speed while managing manufacturing complexity through modular layer-by-layer fabrication processes such as atomic layer deposition (ALD).
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables semiconductor memory devices to operate with a subthreshold swing of 60 mV/dec or less, significantly improving on/off response speed and reducing the GIDL formation time during erase operations, thus enhancing overall device performance and reliability.
Implementation Method 1
a second gate dielectric layer surrounding a part of the first gate electrode, and including a ferroelectric material having negative capacitance in response to a bias applied to the first gate electrode
Implementation Method 2
including a ferroelectric material having negative capacitance
Implementation Method 3
including a ferroelectric material having self-induced negative capacitance
Data Source
AI summary
A switching element comprising: a first gate dielectric layer formed over a substrate; a second gate dielectric layer formed over the first gate dielectric layer to overlap a part of the first gate dielectric layer, and including a ferroelectric material; a second gate electrode formed over the second gate dielectric layer; and a first gate electrode located between the first and second gate dielectric layers, and configured to control the second gate dielectric layer to selectively have negative capacitance.