Vertical Ferroelectric Memory Cells for Multi-Bit High-Density Storage
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Solution Overview
Problem
Ferroelectric memories have limited storage capacity and density due to their small storage capacity per memory cell and difficulty in high-density integration, which restricts their performance improvement and compatibility with fast processor speeds.
Innovation Solution
The ferroelectric memory design includes multiple ferroelectric capacitors per memory cell, arranged perpendicular to the substrate, sharing a common electrode layer to reduce area and enhance integration density, along with a vertical transistor structure to minimize footprint and improve read/write speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If each memory cell stores only one bit of data, then the memory cell structure is simple, but the storage capacity is limited
Solution Approach 1:
The memory cell is segmented into multiple ferroelectric capacitors (first ferroelectric capacitor and second ferroelectric capacitor) arranged in a stacked configuration. Each capacitor can store one bit of data, and their combination enables multi-bit storage capacity within a single memory cell, resolving the contradiction between storage capacity and structural complexity.
Solution Approach 2:
The patent transitions from a planar arrangement to a three-dimensional stacked configuration of ferroelectric capacitors. By stacking capacitors vertically in the first direction perpendicular to the substrate, the memory cell achieves multi-bit storage capacity while maintaining a compact footprint, effectively resolving the contradiction between storage capacity and device complexity.
2Quantity of substance
If memory cells are arranged in a planar configuration, then the layout is simple, but the storage density is limited
Solution Approach 1:
The patent implements a three-dimensional stacked arrangement where multiple ferroelectric capacitors are positioned vertically in the first direction perpendicular to the substrate. This vertical stacking dramatically increases storage density by utilizing the third dimension, while the shared electrode layer simplifies the overall structure, resolving the contradiction between storage density and device complexity.
Solution Approach 2:
Adjacent ferroelectric capacitors share a common first electrode layer that extends in the first direction. This merging of electrode structures reduces the total number of electrodes required, simplifies the memory cell arrangement, and enables efficient vertical stacking to achieve high storage density without excessive structural complexity.
3Area of stationary object
If each ferroelectric capacitor has separate electrode layers, then the capacitor structure is complete, but the memory cell area is large
Solution Approach 1:
The patent merges the first electrode layers of adjacent ferroelectric capacitors into a single shared first electrode layer that extends in the first direction. This consolidation reduces the total electrode count and material usage while maintaining complete capacitor structures, effectively resolving the contradiction between memory cell area and device complexity.
Solution Approach 2:
The shared first electrode layer serves multiple functions: it acts as the first electrode for multiple adjacent ferroelectric capacitors simultaneously, provides electrical connection to the transistor, and extends vertically to enable three-dimensional stacking. This multi-functionality reduces the overall memory cell area while maintaining structural completeness.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design increases storage capacity and density, enabling faster read/write speeds and higher integration density, thus improving overall memory performance and compatibility with high-speed processors.
Implementation Method 1
Any ferroelectric capacitor includes a first electrode layer, a second electrode layer, and a ferroelectric layer formed between the first electrode layer and the second electrode layer
Data Source
AI summary
A ferroelectric memory includes a substrate and a plurality of memory cells formed on the substrate. Each memory cell includes a transistor and a plurality of ferroelectric capacitors. In other words, each memory cell includes at least two ferroelectric capacitors to implement multi-bit data storage. The transistor and the plurality of ferroelectric capacitors are arranged in a first direction perpendicular to the substrate. Any ferroelectric capacitor includes a first electrode layer, a second electrode layer, and a ferroelectric layer formed between the first electrode layer and the second electrode layer. The first electrode layers of every two adjacent ferroelectric capacitors of the plurality of ferroelectric capacitors are in contact, to form a shared first electrode layer that extends in the first direction.