Semiconductor Output Driver for Pad Coupling Verification
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in verifying the coupling state of pads coupled to external resistors after packaging, which complicates impedance calibration due to changing PVT conditions and potential impedance mismatching, leading to signal integrity issues.
Innovation Solution
A semiconductor integrated circuit is designed with a comparison unit that generates first and second comparison signals by comparing the pad voltage with upper-limit and lower-limit reference voltages, and an output driver unit that drives these signals with pull-up and pull-down codes to output data, allowing verification of the coupling state of the pad, even after packaging.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If source termination is performed by an output circuit and parallel termination is performed by a termination circuit, then impedance matching is achieved, but the resistance value changes depending on PVT conditions requiring complex calibration circuits
Solution Approach 1:
The ODT circuit performs self-calibration by using its own internal resources (pull-up/pull-down units and counters) to automatically adjust and equalize resistance values without requiring external calibration circuits or additional components
Solution Approach 2:
The ODT circuit integrates multiple functions including termination, calibration, and verification capabilities into a single circuit block, eliminating the need for separate calibration circuits and enabling both impedance matching and self-verification
2Reliability
If the ZQ pin is used for impedance calibration, then resistance values are equalized to external resistor, but the pad cannot be tested after packaging
Solution Approach 1:
The ODT circuit uses feedback mechanisms where comparison units continuously monitor pad voltages and feed this information back to control units, which adjust pull-up/pull-down unit resistances to maintain proper impedance calibration and verify pad coupling status
Solution Approach 2:
The invention introduces internal verification signals and comparison units that act as intermediaries to indirectly verify the pad coupling state by monitoring voltage levels and calibration results, eliminating the need for direct external pin testing
3Speed
If signal swing width is reduced to increase data transmission rate, then DDR operation is enabled, but external noise effect increases and signal integrity deteriorates
Solution Approach 1:
The ODT circuit applies preliminary termination resistance matching at both transmission and reception stages to prevent signal reflections and reduce the impact of external noise before they can affect signal integrity, enabling reliable DDR operation
Data Source
AI summary
A semiconductor integrated circuit includes a first output driver configured to drive a first comparison signal, which is generated by comparing a voltage of a pad coupled to an external resistor with an upper-limit reference voltage, according to drivability determined by a pull-up code and a pull-down code, and output the driven signal as first output data; and a second output driver configured to drive a second comparison signal, which is generated by comparing the voltage of the pad with a lower-limit reference voltage, according to the drivability determined by the pull-up code and the pull-down code, and output the driven signal as second output data.