Vertical 2T Memory Cell Layout for Higher-Density Shared Access Lines
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Solution Overview
Problem
Conventional volatile memory devices face challenges in reducing memory cell size to increase storage density due to physical limitations and fabrication constraints, limiting their ability to shrink further.
Innovation Solution
The development of a memory device with a 2T memory cell structure, where each cell includes two transistors formed vertically over a semiconductor substrate, allowing for a smaller footprint and improved storage density through a floating-gate based charge storage structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional memory cell structures are used to increase storage density, then device storage density improves, but physical limitations and fabrication constraints prevent further shrinking
Solution Approach 1:
The patent transitions from planar 2D memory cell layout to a 3D vertical architecture where transistors are stacked above the substrate. The word line extends vertically through multiple transistor gates, enabling three-dimensional integration and significantly reducing the footprint per memory cell while maintaining electrical functionality.
Solution Approach 2:
The shared word line structure serves multiple functions: it acts as a control electrode for selecting memory cells during read operations, a control electrode for write operations, and a common reference for multiple transistors in the vertical stack. This multi-functionality reduces the number of separate conductors needed, further compacting the cell design.
2Area of stationary object
If memory cell size is reduced to increase storage density, then device area utilization improves, but fabrication constraints make further shrinking difficult
Solution Approach 1:
By stacking transistors vertically above the substrate rather than arranging them in-plane, the patent achieves higher integration density without requiring proportionally smaller feature sizes. The vertical dimension provides additional space for transistor channels and gates, effectively decoupling area reduction from feature size scaling.
Solution Approach 2:
The patent implements a nested structure where the first transistor is formed with its channel and gate, then the second transistor is formed directly above it with overlapping vertical positioning. The word line penetrates through both transistor gates, creating a compact nested arrangement that maximizes space utilization.
3Quantity of substance
If vertical transistor stacking is implemented to reduce footprint, then storage density improves, but read/write operation complexity increases
Solution Approach 1:
The shared word line is designed to perform multiple functions: selecting memory cells for read operations, selecting memory cells for write operations, and providing a common control signal to both transistors in the vertical stack. This universal control mechanism simplifies the overall operation control logic despite the vertical complexity.
Solution Approach 2:
The patent separates read and write operations into distinct operational phases with different voltage applied to the word line and bit lines. During read operations, the word line is activated to enable current flow through the selected transistor to the bit line. During write operations, different voltage combinations are applied to force current flow in the desired direction. This temporal segmentation of operations manages complexity.
Data Source
AI summary
Some embodiments include apparatuses and methods operating the apparatuses. One of the apparatuses includes a first data line located over a substrate, a second data line located over the first data line, a third data line located over the second data line and electrically separated from the first and second data lines, and a memory cell coupled to the first, second, and third data lines. The memory cell includes a first material between the first and second data lines and electrically coupled to the first and second data lines; a second material located over the first data line and the first material, the second material electrically separated from the first material and electrically coupled to the third data line; and a memory element electrically coupled to the second material and electrically separated from the first material and first and second data lines.