I/O Bank Byte Clock Architecture for Lower Jitter and Skew
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Solution Overview
Problem
Conventional I/O bank architectures in integrated circuits rely on global clocks, which are subject to loading effects that induce jitter and delay, reducing the accuracy and reliability of synchronous interfaces.
Innovation Solution
The proposed I/O bank architecture includes locally generated clock resources within the I/O bank, utilizing phasers and a physical interface controller to manage clock signals independently for each byte clock group, minimizing jitter and enhancing performance by restricting the number of pins controlled by each clock resource.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If global clocks are used to clock I/O bank circuits, then the clock signal can be distributed to multiple pins, but loading effects induce jitter and delay reducing accuracy and reliability
Solution Approach 1:
The I/O bank is divided into multiple byte clock groups (e.g., four groups), with each group having its own dedicated clock resource. This segmentation isolates the clock signals so that each clock resource controls only a limited number of pins, preventing loading effects from affecting the entire bank. The segmentation directly addresses the harmful loading effects by creating independent clock domains.
Solution Approach 2:
Each byte clock group is equipped with local clock resources (phasers and FIFOs) that generate and manage clock signals specifically for that group's pins. This local quality ensures that clock signals are generated close to where they are needed, minimizing transmission delays and jitter. The local clock resources provide tailored clocking without being affected by global loading effects.
2Measurement precision
If locally generated clock resources are used within the I/O bank, then jitter and delay are minimized improving accuracy, but the device complexity increases
Solution Approach 1:
The clocking function is segmented into multiple independent byte clock groups, each with its own phaser and FIFO resources. This segmentation distributes the complexity across multiple manageable units rather than requiring a single complex global clock system. Each segment handles a subset of pins, making the overall system complexity more tractable.
Solution Approach 2:
The phaser and FIFO resources are designed as universal components that can be replicated across multiple byte clock groups. Each byte clock group uses the same architectural pattern (phasers for clock generation, FIFOs for timing management), allowing the system to handle increased accuracy requirements through replication rather than through a single complex design.
Data Source
AI summary
An integrated circuit can include an input/output (I/O) bank. The I/O bank can include a plurality of byte clock groups. Each byte clock group can include at least one phaser configured to clock circuit elements of the byte clock group at a frequency at which a source synchronous device coupled to the byte clock group communicates data.