Vertical Memory Cell Layout With Wavy Word Line Gate Control
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Solution Overview
Problem
Current semiconductor memory devices face challenges in integrating vertical channel transistors effectively, leading to limitations in electrical characteristics and integration density.
Innovation Solution
The semiconductor memory device incorporates a substrate with bit lines, active pillars, and word lines arranged in a specific pattern, including a wavy word line and zigzag active pillars, along with a gate insulating layer and data storage patterns, to enhance integration and electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If vertical channel transistors are used to improve integration density, then integration is improved, but electrical characteristics deteriorate
Solution Approach 1:
The word line is designed with a wavy shape instead of a straight configuration. This curvature allows the word line to better conform to the vertical active pillars, improving gate control over the channel while maintaining high integration density. The wavy pattern increases the effective gate coverage area without increasing device footprint, thus resolving the contradiction between integration and electrical performance.
Solution Approach 2:
The invention transitions from a planar two-dimensional layout to a three-dimensional vertical structure. Active pillars extend vertically from the substrate, and the word line wraps around them in a wavy pattern, utilizing the third dimension (height) to achieve both high integration density and improved electrical characteristics through better gate control.
2Power
If vertical channel transistors are used to improve current driving capability, then current driving capability is improved, but device complexity increases
Solution Approach 1:
The device is segmented into distinct vertical components: active pillars rising from the substrate, gate insulating layers wrapped around the pillars, and wavy word lines that follow the pillar contours. This segmentation allows each component to be optimized independently for current driving capability while the modular structure manages complexity through standardized repeating units.
Solution Approach 2:
The vertical channel transistor employs composite material structures including gate insulating layers (such as high-k dielectrics) combined with conductive word lines, and active pillars made from semiconductor materials. This composite approach enhances current driving capability through improved electrical properties while the layered composite structure provides a systematic way to manage device complexity.
Data Source
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AI summary
A semiconductor memory device may include a plurality of bit lines (BL) extending in a first direction on a substrate (SUB), a plurality of active pillars (ACP) respectively on the bit lines (BL), a word line (WL) extending in a second direction along the plurality of active pillars (ACP), a plurality of landing pads (LP) respectively on the plurality of active pillars (ACP), and a plurality of data storage patterns (DSP) respectively on the plurality of landing pads (LP). Each of the plurality of active pillars (ACP) may have a length extending in a direction perpendicular to an upper surface of the substrate (SUB). The word line (WL) has a wavy shape when viewed in a plan view.