3D Memory Stack Integration for Logic-Safe Microelectronic Fabrication
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Solution Overview
Problem
Conventional microelectronic device designs face challenges in reducing feature dimensions and separation distances while maintaining performance and simplifying fabrication, particularly due to processing conditions affecting control logic devices in memory devices.
Innovation Solution
A method for forming microelectronic devices that includes forming vertical memory arrays with sacrificial structures and insulative structures in tiers, along with control logic devices on a base structure, allowing for reduced size and improved performance by integrating control logic circuitry with memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional vertical memory array architectures are used to increase memory density, then integration and density of features are improved, but processing conditions limit the configurations and performance of control logic devices
Solution Approach 1:
The device is divided into distinct segments: a first substrate containing control logic devices, and a second substrate containing the vertical memory array. This segmentation allows independent optimization of each substrate, enabling high memory density on the second substrate while maintaining control logic device performance on the first substrate under suitable processing conditions.
Solution Approach 2:
A bonding interface acts as an intermediary between the first substrate (control logic) and the second substrate (memory array). This intermediate structure enables the two substrates to be combined while preserving the processing conditions and performance characteristics of the control logic devices on the first substrate.
2Area of stationary object
If the quantities, dimensions, and arrangements of control logic devices are reduced to decrease device size, then horizontal footprint is reduced, but performance such as memory cell ON/OFF speed and threshold switching voltage deteriorates
Solution Approach 1:
The control logic devices are arranged in a three-dimensional configuration with vertical stacking, allowing multiple control logic devices to be positioned at different vertical levels. This vertical arrangement reduces the horizontal footprint while maintaining adequate spacing and performance characteristics for each control logic device.
Data Source
AI summary
A method of forming a microelectronic device comprises forming a first microelectronic device structure comprising a preliminary stack structure comprising sacrificial structures and insulative structures vertically alternating with the sacrificial structures. A second microelectronic device structure comprising control logic circuitry is formed. The first microelectronic device structure is attached to the second microelectronic device structure to form an assembly. After forming the assembly, the sacrificial structures are at least partially replaced with conductive structures to form a stack structure. Contact structures are formed to extend through the stack structure. One or more of the contact structures are coupled to the control logic circuitry. Conductive line structures are formed over the stack structure. One or more of the conductive line structures are coupled to the one or more of the contact structures. Microelectronic devices, memory devices, and electronic systems are also described.