3D Memory Stack Layout for Density and Voltage Isolation
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Solution Overview
Problem
Planar memory cells face density limitations and scaling challenges, leading to increased costs and complexity in manufacturing, while traditional 3D memory architectures struggle with inefficient use of planar space and high voltage requirements.
Innovation Solution
A 3D memory device architecture with vertically stacked DFM and NAND memory cell arrays and peripheral circuits, each with different voltage requirements, is fabricated on separate substrates and bonded together, allowing for independent thermal budgets and reduced planar size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar memory cells are scaled to smaller sizes to increase density, then memory density improves, but manufacturing complexity and cost increase significantly
Solution Approach 1:
The patent transitions from planar (2D) memory cell scaling to three-dimensional stacked architecture, where memory cells are arranged vertically across multiple layers. This dimensional change allows continued density improvement without the manufacturing complexity penalties of extreme planar scaling, as each layer can use more conventional process nodes while achieving higher overall density through vertical stacking.
Solution Approach 2:
The memory device is divided into multiple semiconductor layers (first through fourth layers), each containing specific memory cell arrays or peripheral circuits. This segmentation allows different layers to be optimized independently for their specific functions, with varying transistor types and voltage requirements, thereby reducing overall manufacturing complexity while maintaining high density.
2Quantity of substance
If traditional 3D memory architecture is used to increase density, then memory density improves, but planar space utilization becomes inefficient
Solution Approach 1:
The patent employs a three-dimensional stacked architecture where memory cell arrays are distributed across multiple vertical layers rather than being confined to a single planar layer. This enables efficient utilization of both planar footprint and vertical height, achieving high density without wasting planar space, as each layer contributes to the overall storage capacity within the same lateral footprint.
3Reliability
If high voltage requirements are maintained in 3D memory architecture, then memory operational capability is preserved, but device complexity increases
Solution Approach 1:
Different semiconductor layers are equipped with different transistor types optimized for their specific voltage requirements. High-voltage transistors are placed only where needed (in layers requiring high voltage for memory operations), while other layers use standard low-voltage transistors. This localized optimization maintains the necessary high-voltage operational capability while reducing overall device complexity and power consumption.
4Ease of manufacture
If all memory cell arrays and peripheral circuits are fabricated on the same substrate, then manufacturing process is simpler, but thermal management and voltage isolation become challenging
Solution Approach 1:
The patent separates memory cell arrays and peripheral circuits into different semiconductor layers, allowing independent thermal management and voltage isolation for each layer. This segmentation enables different thermal budgets and voltage domains to be handled independently, simplifying thermal management and voltage isolation while maintaining manufacturing feasibility through sequential fabrication and bonding processes.
Data Source
AI summary
Three-dimensional (3D) memory devices and fabricating methods are disclosed. A disclosed 3D memory device can comprises, a first semiconductor structure comprising an array of first type memory cells, a second semiconductor structure comprising an array of second type memory cells different from the first type memory cells, a third semiconductor structure comprising a first peripheral circuit, and a fourth semiconductor structure comprising a second peripheral circuit. The third semiconductor structure and the fourth semiconductor structure are sandwiched between the first semiconductor structure and the second semiconductor structure in a vertical direction.