3D Memory Cell Stack Layout for RC Delay and Reliability
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Solution Overview
Problem
The operational reliability of three-dimensional semiconductor devices deteriorates as the number of stacked memory cells increases, limiting integration and performance.
Innovation Solution
The semiconductor device incorporates conductive layers and interlayer insulating layers alternately stacked with select conductors, outer and inner auxiliary conductors surrounding cell plugs, and select protrusions to enhance structural integrity and reduce RC delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the stacked number of memory cells is increased to improve the degree of integration, then the area occupied by memory cells per unit area is reduced, but the operational reliability of the three-dimensional semiconductor device deteriorates
Solution Approach 1:
The semiconductor device is divided into multiple stacked memory cell layers, with each layer being a separate functional unit. This segmentation allows high integration through stacking while maintaining operational reliability by isolating potential failure points to individual layers rather than affecting the entire device.
Solution Approach 2:
Interlayer insulating layers are introduced as intermediary structures between adjacent memory cell layers and conductive layers. These intermediary layers provide electrical isolation and mechanical support, enabling increased stacking density while preventing signal interference and maintaining the stability of each memory cell layer, thus preserving operational reliability.
2Productivity
If the stacked number of memory cells is increased, then more memory cells can be integrated in three-dimensional space, but read operation stability deteriorates due to increased RC delay
Solution Approach 1:
The patent transitions from planar two-dimensional memory cell arrangement to three-dimensional stacking architecture. By utilizing the vertical dimension for stacking multiple memory cell layers, the device achieves higher integration density while the interlayer insulating layers provide electrical isolation that mitigates RC delay effects between layers, maintaining read operation stability.
Solution Approach 2:
Interlayer insulating layers serve as intermediary structures between stacked memory cell layers and conductive layers. These layers reduce parasitic capacitance and resistance by providing proper electrical isolation, thereby decreasing RC delay and maintaining read operation stability even as the number of stacked memory cells increases.
Data Source
AI summary
A semiconductor device includes: conductive layers and interlayer insulating layers, which are alternately stacked; a select conductor spaced apart from the conductive layers; cell plugs penetrating the conductive layers, the interlayer insulating layers, and the select conductor; and an auxiliary conductor in contact with the select conductor.