3D Semiconductor Memory Device With Vertically Stacked Electrodes
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving high integration density and reliability due to the limitations of two-dimensional (2D) designs, which require expensive and advanced equipment for fine pattern formation, leading to the development of three-dimensional (3D) semiconductor memory devices to increase integration density.
Innovation Solution
The proposed 3D semiconductor memory device includes a peripheral logic structure with a well plate electrode, a semiconductor layer, and vertically stacked electrodes, along with a data storage layer and interconnection structures, to enhance integration density and reliability, featuring a cell array structure with common source regions and a voltage generator for efficient operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If two-dimensional (2D) or planar semiconductor device design is used, then manufacturing process is simpler, but integration density is limited
Solution Approach 1:
The patent transitions from two-dimensional planar device architecture to three-dimensional vertically stacked architecture. Multiple memory cells are stacked vertically along the third dimension, with word lines, bit lines, and charge storage structures arranged in multiple layers. This dimensional change enables significantly higher integration density without requiring proportionally more complex manufacturing processes, as the vertical stacking can be achieved through sequential deposition and patterning steps.
2Quantity of substance
If fine pattern formation techniques are advanced to increase 2D device density, then integration density improves, but equipment cost and complexity increase
Solution Approach 1:
Instead of continuing to push the limits of two-dimensional pattern scaling which requires increasingly advanced and expensive lithography equipment, the patent moves to three-dimensional stacking. This approach achieves higher density through vertical arrangement of memory cells, word lines, and bit lines, thereby avoiding the need for extremely advanced lithography tools while still attaining superior integration density.
3Quantity of substance
If three-dimensional (3D) vertically stacked structure is implemented, then integration density increases, but manufacturing complexity increases
Solution Approach 1:
The three-dimensional memory structure is segmented into distinct functional layers including word line structures, bit line structures, charge storage structures, and insulation layers. Each segment can be formed through separate deposition and patterning steps, allowing for modular manufacturing. The vertical stacking is achieved by sequentially forming these segmented components, which simplifies the overall manufacturing process compared to attempting to form the entire 3D structure in a single step.
Solution Approach 2:
The patent employs preliminary actions in the manufacturing sequence by first forming the semiconductor substrate and initial insulation layers, then sequentially depositing and patterning word lines, followed by bit lines, and finally charge storage structures. This preliminary arrangement of lower-layer components provides a structured foundation that guides subsequent manufacturing steps, reducing overall manufacturing complexity despite the three-dimensional final structure.
Data Source
AI summary
A three-dimensional (3D) semiconductor memory device that includes a peripheral logic structure including peripheral logic circuits disposed on a semiconductor substrate and a first insulation layer overlapping the peripheral logic circuits, and a plurality of memory blocks spaced apart from each other on the peripheral logic structure. At least one of the memory blocks includes a well plate electrode, a semiconductor layer in contact with a first surface of the well plate electrode, a stack structure including a plurality of electrodes vertically stacked on the semiconductor layer, and a plurality of vertical structures penetrating the stack structure and connected to the semiconductor layer.