3D Non-Volatile Memory Stacked Conductive Layer Patterning
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Solution Overview
Problem
Two-dimensional memory devices have reached physical limits in increasing integration, necessitating the development of three-dimensional non-volatile memory devices with stacked memory cells, which require efficient patterning of conductive layers to selectively drive memory cells.
Innovation Solution
A semiconductor device with a substrate featuring stacked conductive layers and strategically placed slits to pattern the first conductive layer into multiple units, allowing for the formation of memory blocks and contact regions, enabling efficient patterning and improved integration through a self-aligned process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If two-dimensional memory devices are used, then manufacturing process is simple, but degree of integration reaches physical limits
Solution Approach 1:
The patent transitions from two-dimensional memory cell arrangement to three-dimensional stacked structure, where memory cells are arranged vertically across multiple layers. This dimensional change allows significant increase in storage capacity without proportionally increasing footprint area, thereby overcoming the integration density limits of planar devices while maintaining manufacturing feasibility through adapted fabrication processes.
2Quantity of substance
If stacked conductive layers are added for 3D structure, then degree of integration increases, but patterning complexity increases
Solution Approach 1:
The patent divides the conductive layers into multiple segmented regions with different patterns, where each segment can be independently controlled. This segmentation allows selective activation of specific memory cells or blocks, simplifying the control logic for complex 3D structures and enabling modular fabrication approaches that reduce overall patterning complexity.
Solution Approach 2:
The patent employs preliminary patterning actions during fabrication, where conductive layers are pre-patterned into specific configurations before final device assembly. This preliminary structuring simplifies subsequent processing steps and reduces the complexity of final patterning operations by preparing the structure in advance.
3Ease of operation
If conductive layers are patterned to selectively drive memory cells, then memory cell access improves, but manufacturing difficulty increases
Solution Approach 1:
The patent implements local quality variations in the conductive layers, where different regions have different conductivity patterns, thicknesses, or material compositions tailored to specific functional requirements. This allows optimized memory cell access in different areas of the device while maintaining overall manufacturing feasibility through standardized processing techniques adapted to local needs.
Data Source
AI summary
A semiconductor device includes at least one first conductive layer stacked on a substrate where a cell region and a contact region are defined; at least one first slit passing through the first conductive layer, second conductive layers stacked on the first conductive layer; a second slit passing through the first and second conductive layers and connected with one side of the first slit, and a third slit passing through the first and second conductive layers and connected with the other side of the first slit.