Solid-State Devices TRIZ Cases

Grouped TSV connections spread power evenly across stacked dies, reducing current concentration, electromigration, and via wear.

Multiple semiconductor chips and conductive channels are combined in one package to improve multi-channel surge and ESD protection.

A recessed inorganic encapsulation layer improves light entry into the wavelength conversion layer and broadens display viewing angles.

By routing the GOA circuit on the substrate backside through via holes, this case frees display-region wiring space and raises pixel transmittance.

Stacked storage electrodes and mixed poly-silicon/oxide TFTs raise subpixel capacitor capacity in high-resolution displays.

A nested opening and isolation structure raises chip pad density while reducing TSV stress and yield loss in compact semiconductor packaging.

Adjacent sensing circuits share power and signal lines to preserve pixel aperture ratio while supporting both display and sensing.

A random duty cycle clock limits charge pump input current during voltage ramp-up, then switches to voltage regulation for faster memory operation.

Grooves extending to array-substrate via-holes guide orientation liquid evenly, preventing buildup and improving LCD coating yield and picture quality.

Trap elements in dielectric layers absorb hydrogen before it reaches the oxide semiconductor, stabilizing TFT threshold voltage and reliability.

Wafer-to-wafer hybrid bonding enables dense GaN LED arrays, while quantum dot color conversion adds efficient green and red output for ocular displays.

Convex portions and light-reflecting resin reduce joint voids and raise luminance contrast for better LED light extraction.

Routing signal lines around transparent areas cuts reflective metal, reducing light scattering and improving transmittance and image clarity.

Varying solder layer thickness lets different-color subpixel LEDs bond without interference, raising substrate density and lowering display cost.

Vertical memory strings with pillar semiconductors and shared conductor layers raise NAND density while cutting lithography steps and short-circuit risk.

A double SOI fin stack enables precise channel height and insulation control, raising CFET transistor density without extreme fin aspect ratios.

A sub-bank surrounded by an intermediate electrode improves pixel connection reliability and supports more uniform light emission.

GaN HEMT inverter structures cut FPGA power loss and waste heat while supporting higher switching frequency for AI driving workloads.

Via-defined pixels and carrier diffusion enable monolithic RGB micro-LED arrays with tighter pitch, lower etch damage, and no pick-and-place assembly.

A stepped adjustment layer with edge unevenness helps handle tiny micro LEDs as unit pixel modules, improving mounting stability and installation reliability.

Vertical conductor and insulator stacks shrink structured light emitters while improving spatial control for compact biological examination use.

Transparent N and P materials improve visible-range exciton dissociation and charge transfer while preserving transparency in organic image sensors.

Mixing fullerene-based materials with different particle sizes densifies the organic layer, cuts voids, and helps prevent electrode short circuits.

Segmented silicide-covered gate regions and spacers improve overlay control, cut gate resistance, and reduce switching loss in power MOSFETs.

Selective dummy-region isolation and stacked contact plugs prevent bit-line shorts and protect capacitor alignment in DRAM cells.

Correcting standard pixels beside mixed OCL shapes helps CMOS image sensors suppress flat-area artifacts and stabilize image quality.

A floating third electrode reshapes the electric field to control emitter alignment density, raising luminance per area while enabling smaller pixels.

Thickness-graded pixel defining layers guide inkjet-printed OLED films to improve layer uniformity and prevent color mixing between pixels.

Partial isolation between adjacent photodiodes improves angular selectivity and light sensitivity uniformity for phase detection autofocus.

A vertical transfer gate and insulation wall improve charge transfer in backside image sensor pixels by avoiding local potential minima.

An F, Cl, and C containing auxiliary layer supplies carriers to oxide semiconductor TFTs, raising on-current without sacrificing gate insulation.

A dielectric-lined top electrode and amorphous hard masks cut MTJ edge roughness and prevent ferromagnetic-layer shorts in MRAM fabrication.

Inclined inverted-trapezoidal DBR through-holes improve light reflection and electrode coverage in micro LEDs while reducing metal fracture risk.

A spacer confines metal residue at the memory element interface, preventing interference with nearby logic and other circuitry.

Object-side telecentric microlenses and light blocking members keep visual fields aligned, improving depth of field and image reading accuracy.

A support substrate and laser-broken joint member let thinned wafers be peeled and transferred with lower breakage and pattern damage.

Hybrid oxide-silicon TFT pixels cut leakage while preserving switching speed and uniformity in OLED and LCD displays.

A multilayer asymmetric electrode layout strengthens electric fields at LED placement sites while suppressing stray fields to improve display self-assembly yield.

A grounded charge release layer drains trapped carriers from dielectric grid structures, reducing dark current and white pixel defects.

A widened non-overlapping gate insulation edge suppresses strong drain-gate fields, stabilizing on-current and threshold voltage at high voltage.

Deep and shallow trench isolation with asymmetric corner radii improves pixel pattern yield and reduces crosstalk in CMOS image sensors.

Matching cap substrate thickness to top-die warpage helps HBM stacks avoid bonding voids and maintain reliable electrical connections.

Spaced layer edges in the non-display area make electrode, protection, and encapsulation boundaries easier to inspect and deposit accurately.

Deep-LUMO p-type doping matched to deep-HOMO hole transport materials cuts OLED voltage and extends lifetime by removing extra layers.

A planarization layer flattens large step differences so photosensitive devices can overlap pixel circuits and improve X-ray detection efficiency.

Vertical hybrid bonding places SRAM above the processor to shorten cache interconnects, cutting RC delay, chip size, and transfer latency.

Rigid LED mounting boards paired with a lower-rigidity wiring board enable bendable display illumination without sacrificing heat and light durability.

By splitting wavelengths instead of absorbing them in color filters, this lens array directs light to matching pixels and improves sensor light use.

Independent red, blue, and green phosphor LEDs tune white light across 2700-6500 K while preserving high CRI, R9, and color preference.

An etchant-resistant organic layer shields semiconductor rods during lift-off, preserving smooth surfaces and reducing contact or emission failures.

Series storage capacitors reduce pixel RC delay and data read-out time in X-ray detectors.

Nitrogen heterocyclic ring improves molecular overlap and stability while maintaining solubility.

A display medium divides flat members into unit cells and subcells with projecting members to express content colors via microcells.

An opaque shielding layer over imager peripheral circuitry blocks radiant energy to eliminate column-banding noise artifacts.

A parallel detection unit generates output signals representing electrostatic discharge counts without increasing circuit footprint.

Hemispherical groove structures on glass substrates redirect emitted light to reduce refraction angles and increase luminous efficiency.

Bank structures isolate micro light-emitting diodes in accommodating regions, reducing optical cross-talk and improving contrast.

Self-aligned sidewall spacers define gate trench positions, reducing interval variations and contact resistance inconsistencies.

Non-conductive substrate walls segment pad structures to prevent signal interference, ensuring stable transmission at high resolutions.

UV resin microlenses in photoresist vias protect micro LEDs while enhancing light emission efficiency.

Terminal modification of polyphenylene oxide removes hydroxyl groups to resolve the contradiction between ease of manufacture and device reliability.

A single critical mask defines multiple trench depths in a semiconductor substrate to form vertical transfer gates and isolation structures.

Segmented bit line architecture increases cell transistor gate width to triple reading speed without expanding circuit area.

A programmable logic device uses a serial peripheral interface port to transfer configuration data between volatile and non-volatile memory.

A semiconductor module maintains controlled wavelength deviation across panel substrate regions to ensure consistent light emission.

Segmented insulating layers with a groove barrier isolate the buffer area from the functional display region in OLED substrates.

A display unit uses a segmented charge injection-transport layer to block current leakage between adjacent pixels.

Direct drain electrode connections eliminate narrow bridge electrodes, preventing etching defects and improving manufacturing yield.

A semiconductor channel doping method uses distinct dopant types for edge and center regions to enhance electrical performance.

An electrically-conductive component within an RRAM cell enables precise resistance differentiation across multiple programmable states.

Segmented buffer and filling layers penetrate active layer voids to limit parasitic leakage currents without increasing manufacturing complexity.

A vertical resistive switching device uses a conductive alloy electrode to control oxygen vacancy formation in the filament region.

Foldable portions in a touch flexible printed circuit reduce length via bending silkscreen lines, eliminating bonding damage and improving accuracy.

A fingerprint sensing device integrates a spacer layer with main spacers to stabilize spacing between micro-lens structures and sensing elements.

Pillar structure with insulator strips reduces NAND flash memory cell area, resolving isolation challenges between channels and source/drain regions.

A light emitting device package places a metal plate between the semiconductor and package body to lower thermal resistance.

Branches on common electrode lines block interference from data line electric fields, reducing light leakage and improving display quality.

A functional layer on a display cover plate modulates laser intensity to ensure uniform heating of the glass adhesive.

Segmented display units with local shielding structures prevent adjacent light mixing while maintaining high brightness and color saturation.

Non-volatile memory cells use a transition metal oxide layer with excess metal content to reduce operation voltage and improve patterning uniformity.

A semiconductor device uses protective layers around a narrower variable resistance pattern to maintain structural integrity during manufacturing.

A capacitor uses a rough top electrode surface to increase capacitance without expanding the device footprint.

Electromagnetic wave guiding element with higher refractive index focuses light onto photo-sensing elements.

Replacing wire bonding with through silicon vias in a stacked MEMS microphone package frees space reserved for external connections, reducing overall volume.

A barrier layer protects the substrate during optical pattern formation in fingerprint sensor displays.

Segmenting the light emitting layer via a bank hole and groove pattern blocks leakage current between adjacent subpixels to maintain image quality.

Dual etching patterns MRAM resistance switching elements for fast programming and stable data retention.

A salicide layer forms a Schottky diode with the conductive pillar in 3D memory stacks.

A 3D nonvolatile memory structure uses gate electrodes with varying thicknesses to optimize electric field distribution across vertical channel layers.

Barrier ribs with closed loop shapes reflect stray light while a high-index planarization layer condenses it, improving frontal visibility.

Extending the word line directly to a protective diode maintains reverse voltage across the pn junction, preventing charge injection into the storage layer.

A vertical semiconductor pillar uses a lattice mismatch between inner and outer regions to induce tensile stress in the channel.

A dual-structured OLED display frame uses a cap to cover panel gaps, eliminating the need for an additional exterior case.

A partitioning wall separates organic layer forming and non-forming regions on a display substrate, preventing material flow into terminal areas.

Polycyclic aromatic hydrocarbon copolymers enable high mobility in flexible organic thin film transistors.

Segmented phase-change layers enable void-free burial in narrow regions, boosting integration density without high-temperature processing.

Segmenting the electron transport layer into distinct sub-layers resolves lifetime versus stability contradictions while sustaining efficient charge injection.

Segmenting packaging adhesive inside and outside a cover plate groove resolves the contradiction between thin spacer requirements and sealing reliability.

Dielectric microlens arrays prevent organic photoresist damage and particle absorption to improve image quality.

A second display panel with a light absorption pattern partitions OLED emissive areas into sub-emissive zones to reduce external light reflection.

A silicone-modified adhesive layer stabilizes bonding strength over time, preventing wafer damage and contamination during thin wafer backgrinding.

Replacing transparent conductive materials with opaque metal pixels resolves low contrast ratios by clearly separating light paths.

Multiple light emitting regions connect in series via intermediate pads to enable versatile brightness control.

A solidification inhibiting layer prevents sealant from spreading onto spacers, maintaining layer contact precision and boosting manufacturing yield.

Bulging memory stack structures expand contact areas with source strap structures to enhance electrical connectivity in three-dimensional devices.

A common electrode connection line joins multiple pixel unit electrodes through a single shared via hole structure.

Timed voltage control on select transistors minimizes peak current flow and stabilizes threshold voltages during read operations.

Segmenting the active region into isolated micro-channels prevents uncontrollable micro-sparkovers while maintaining high signal amplification.

Matching select transistor pitch to core memory cell pitch eliminates wasted space in the transition interface, improving wafer utilization.

Bent wiring film connects pad units through substrate indentations to integrate components without overlapping the display area.

Specific dibenzofuran and dibenzothiophene bonding positions on biscarbazole compounds resolve performance variability to extend device lifetime.

Impurity doping transforms resistance variable elements into conductive contacts, eliminating complex masking and etching steps to simplify fabrication.

Stacked conductive layers use strategic slits to define memory blocks and contact regions for efficient patterning.

Rear-surface circuit pattern recognition aligns dicing cuts on a layered wafer stack, preventing adhesive scattering and contamination during singulation.

Concentric arc-shaped pixel electrode units distribute voltage uniformly to align liquid crystal molecules isotropically around thin film transistors.

An L-shaped second gate conductor reduces spacing between adjacent gates while maintaining electrical isolation through inter-gate dielectric structures.

Centralizing gate and storage lines in the reflection region eliminates bridge structures, preventing aperture loss and irregular liquid crystal alignment.

Segmented flared source structures prevent defects during manufacturing, improving yield and electrical characteristics in high-density memory devices.

Vertical gate stacking increases storage capacity without expanding the planar area occupied by peripheral circuits and wiring.

A 3D memory structure uses intersecting electrode planes and pillars to enable high-density storage with reduced manufacturing complexity.

A conformal dielectric liner protects recessed regions in ultra-thin semiconductor-on-insulator substrates during processing.

A solid-state x-ray detector couples a second semiconductor device to maintain photodiode bias voltage without periodic scrubbing.

A data latch circuit uses a common gate structure to reduce transistor count and physical footprint in semiconductor memory devices.

Tapered spacers on the pixel definition layer guide mask plate placement during vapor deposition to improve alignment accuracy.

Adjusting nonmagnetic spacer thickness optimizes interlayer exchange coupling, enabling high-speed magnetization reversal with reduced writing current.

A lateral electrostatic protection element positions an emitter contact closer to a collector contact than a base contact.

An oxide semiconductor layer with oxygen vacancies allows bidirectional switching, resolving size and selectivity trade-offs in resistive memory arrays.

SONONS hybrid memory cell merges DRAM speed and NVM retention via stacked charge-trapping layers, eliminating refresh cycles.

Dual photodiode imaging element transfers electric charges to holding units for phase difference and time-of-flight detection.

Simultaneous discharge of gallium and dopant targets via reactive sputtering resolves crystallinity trade-offs during layer formation.

Lateral epitaxial growth reduces Miller capacitance and on-resistance in SOI transistors by avoiding vertical source and drain elevation.

Segmenting the mid-frame into a base plate and reinforcing members prevents deformation under external forces while maintaining constant pressure sensitivity.

An expansion sheet uses ultraviolet light to reduce peripheral adhesion for easier detachment from holding units.

An asymmetric pinned layer stabilizes magnetization direction against external magnetic fields, reducing sensing errors in rotation angle detection.

Integrated PN junction diodes in LDMOS structures handle high recirculating currents without external components.

A wire grid polarizer layer sits between two substrates to form a compact display cell structure with integrated pixel electrodes.

A semiconductor device uses trench gate structures and conductive portions to connect source and base layers through an insulating film.

Fluorinated photoresist lithography patterns organic layers uniformly, overcoming screen mask non-planarity in displays exceeding 15 inches.

A 3D lateral channel semiconductor device with a line-shaped common source node stabilizes current discharge.

A voltage-dependent switch circuitry dynamically connects a power FET field plate to reduce output capacitance.

Concentrating signal lines in non-display regions reduces the bezel size and increases the screen-to-body ratio of the display panel.

Strategic well contact plug positioning equalizes dark current across same-color photoelectric conversion units in image sensors.

A chalcogenide memory cell with a narrowed profile concentrates ions to widen the programming window, resolving narrow read margins in phase change devices.

Inserting a zirconium cap layer between the MTJ capping and etch stop layers reduces write error rates while maintaining thermal stability.

A light emitting device uses a recessed reflecting portion to direct emitted light into a collimated beam for improved optical output.

Vertical stacking separates memory arrays from peripheral circuits, reducing lateral footprint while maintaining high data storage capacity.

A vertical field effect transistor incorporates a charge collector dielectric layer to trap radiation charges and modulate threshold voltage.

Segmented double-layer fanout lines prevent light line defects by isolating resistance changes at broken positions within the display panel substrate.

A staggered sub-pixel arrangement aligns white light brightness centers on a straight line, eliminating serrated edges in white patterns.

Peripheral contact between adjacent color filters prevents peeling during thermal shock while hollow portions maintain high light-concentrating efficiency.