Select Transistor Pitch Matching for Semiconductor Density
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Solution Overview
Problem
Non-volatile memory devices face challenges in achieving high density and performance due to the need for small design features and high reliability, with select transistors in the periphery area being formed at a larger pitch than memory cells, leading to wasted space on the semiconductor wafer and a transition interface that consumes valuable space.
Innovation Solution
Select transistors are formed in the periphery area at the same pitch and channel length as memory cells in the core memory array, with extended bit lines from the core memory array to the periphery area, allowing for reduced transition area and efficient use of space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If select transistors are formed at a larger pitch than memory cells, then manufacturing reliability is improved, but wafer space utilization deteriorates
Solution Approach 1:
The patent changes the pitch parameter of select transistors to match the pitch of memory cells in the core array. By forming select transistors at the same pitch (e.g., 10 micrometers) as the memory cells, the invention achieves uniform spacing that improves space utilization while maintaining manufacturing reliability through consistent fabrication parameters across the entire wafer.
Solution Approach 2:
The invention creates a universal pitch standard that serves both memory cells and select transistors. By using the same pitch for both device types, the patent eliminates the need for separate pitch specifications, simplifies the transition interface, and enables uniform manufacturing processes to be applied across different device regions, thereby improving both reliability and space efficiency.
2Area of stationary object
If select transistors are stacked to save space, then wafer space is reduced, but device complexity increases
Solution Approach 1:
Instead of stacking select transistors vertically (using the third dimension), the patent distributes them horizontally across the wafer surface at the same pitch as memory cells. This dimensional approach allows select transistors to be formed in parallel with memory cells rather than stacked above them, reducing device complexity while efficiently utilizing wafer space through lateral arrangement.
3Adaptability or versatility
If a transition interface is created between select transistors and core memory array, then device functionality is enabled, but valuable wafer space is consumed
Solution Approach 1:
The patent merges the pitch parameters of select transistors and memory cells into a unified standard. By forming both device types at the same pitch, the transition interface between the core memory array and periphery select transistors is eliminated or minimized, as the uniform pitch creates natural continuity. This merging of parameters enables device functionality while consuming minimal wafer space for the transition region.
Data Source
AI summary
A semiconductor device includes a core memory array and a periphery area. The core memory array area includes a group of memory cells. The periphery area includes a group of select transistors. The select transistors are formed at substantially the same pitch as the memory cells in the core memory array and with substantially the same channel length.