NAND Flash Memory Pillar Structure for Isolation and Area Reduction
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Solution Overview
Problem
Conventional NAND flash memory arrays with three-dimensional structures face challenges in isolating channels and source/drain regions, and have inefficient processes for cutting floating gates, leading to limitations in reducing cell size and power consumption.
Innovation Solution
A NAND flash memory array with a pillar structure that uses insulator strips and semiconductor strips to form trenches with dielectric layers and sidewall gates, allowing for self-align etching and cost-effective fabrication, enabling improved channel and source/drain isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If conventional three-dimensional structures are used with trenches and sidewalls, then memory cell area is reduced, but isolation between channels and source/drain regions becomes difficult to achieve
Solution Approach 1:
The invention divides the continuous silicon substrate into discrete isolated pillars separated by trenches. Each pillar is independently isolated from adjacent pillars and from source/drain regions through the trench structure filled with dielectric material, achieving both area reduction and proper isolation.
Solution Approach 2:
The invention introduces dielectric material as an intermediary substance filling the trenches between pillars and around source/drain regions. This dielectric layer acts as an electrical insulator that prevents unwanted coupling between adjacent pillars and between channels and source/drain regions.
2Ease of operation
If floating gates are cut in conventional processes, then cell operation is achieved, but manufacturing complexity and cost increase
Solution Approach 1:
The invention extracts the floating gate structure entirely, replacing it with a charge trap layer formed within the dielectric material surrounding each pillar. This eliminates the need for complex floating gate formation and cutting processes while maintaining memory functionality through charge trapping mechanisms.
Solution Approach 2:
The invention changes the fundamental operating parameter from floating gate voltage control to charge trap layer charge state control. By forming the charge trap layer with specific trap density and depth characteristics, the memory cell achieves operation through charge injection and detection rather than floating gate manipulation.
3Ease of manufacture
If planar structures are used, then manufacturing is simpler, but cell size reduction and integration density are limited
Solution Approach 1:
The invention transitions from two-dimensional planar structures to three-dimensional pillar structures by extending the memory cell operation into the vertical dimension. Pillars extend upward from the substrate, allowing multiple cells to be packed into a smaller planar footprint while maintaining manufacturability through vertical processing steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The pillar structure reduces memory cell area by half, enhances integration, and allows for increased silicon pillar height, improving sensing margin and controlling short channel effects, while providing a cost-effective fabrication method.
Implementation Method 1
two or more dielectric layers including a charge trap layer which are formed on both sidewalls and a part of bottom of the each trench
Data Source
AI summary
A method is provided for fabricating a NAND flash memory array having vertical channels and sidewall gate structure and a fabricating method of the same. The NAND flash memory array has insulator strip structure and one or more semiconductor strips are next to the both sides of the insulator strip. The NAND flash memory array allows for an improvement of the integrity by decreasing the memory cell area by half and less, and solves the problems of the conventional three-dimensional structure regarding isolation between not only channels but also source/drain regions at the bottom of trenches. The method for fabricating the NAND flash memory array having a pillar structure uses the conventional CMOS process and an etching process with minimum masks, enables to cut down costs.