3D Nonvolatile Memory With Variable-Thickness Gate Electrodes
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Solution Overview
Problem
Current nonvolatile memory devices face challenges in increasing integration density and performance while maintaining data integrity when power is interrupted, particularly in two-dimensional designs, which can be addressed by developing three-dimensional memory structures.
Innovation Solution
A nonvolatile memory device with a three-dimensional memory array comprising vertically arranged memory cells, including a conductive line, channel layers, and gate electrodes with varying thicknesses and air gaps to enhance integration density and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional memory structure is used, then device complexity is low, but integration density is limited
Solution Approach 1:
The patent transitions from a two-dimensional planar memory structure to a three-dimensional vertical structure. Memory cells are stacked vertically with channel layers extending in the third dimension, allowing multiple memory cells to occupy the same footprint area. This dimensional change dramatically increases integration density while managing device complexity through systematic vertical stacking of components including conductive lines, channel layers, gate electrodes, and air gaps.
2Quantity of substance
If three-dimensional memory structure is used, then integration density is increased, but manufacturing precision requirements increase
Solution Approach 1:
The three-dimensional memory structure is segmented into distinct functional layers including channel layers, gate electrodes, air gaps, and conductive lines. Each layer is formed through separate manufacturing steps with defined thicknesses and positions. The air gaps serve as spacers that define the positioning of adjacent layers, enabling precise layer alignment without requiring extreme manufacturing precision for direct layer-to-layer alignment.
Solution Approach 2:
Air gaps are introduced as intermediary elements between adjacent conductive lines and gate electrodes. These air gaps act as physical spacers that automatically define the spacing and alignment of surrounding structures. By using air gaps as intermediaries, the patent reduces the need for high-precision direct alignment between critical components, as the air gaps provide inherent mechanical positioning references.
3Productivity
If uniform gate electrode thickness is used, then manufacturing is simpler, but performance is limited
Solution Approach 1:
The gate electrodes are designed with non-uniform thickness, where different portions of the same gate electrode have different thicknesses. Specifically, gate electrode portions adjacent to air gaps have different thicknesses compared to portions farther from air gaps. This local variation in thickness optimizes the electric field distribution and control characteristics in different regions, enhancing memory write and read performance while maintaining data integrity during power interruptions.
Data Source
AI summary
A nonvolatile memory device includes a conductive line disposed on a substrate and vertically extended from the substrate, a first channel layer disposed on the substrate and vertically extended from the substrate, wherein the first channel layer is spaced apart from the conductive line, a second channel layer vertically extended from the substrate, wherein the second channel layer is disposed between the first channel layer and the conductive line, a first gate electrode disposed between the conductive line and the second channel layer, wherein the first gate electrode includes a first portion having a first thickness and a second portion having a second thickness that is different from the first thickness, and a second gate electrode disposed between the first channel layer and the second channel layer, wherein the second gate electrode has the second thickness.