Semiconductor Memory Device Select Transistor Voltage Control
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Solution Overview
Problem
Current semiconductor memory devices face challenges in efficiently managing voltage levels during read operations, leading to increased current flow and potential fluctuations in threshold voltage, which affect data accuracy and device performance.
Innovation Solution
The semiconductor memory device employs a specific timing-based voltage control strategy for its select transistors, adjusting voltages of different wiring connections to optimize read operations, ensuring that memory cells are either electrically continuous or in a floating state, thereby minimizing current flow and stabilizing threshold voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If voltage control is applied to select transistors during read operations, then threshold voltage stability is improved, but current flow increases
Solution Approach 1:
The patent applies preliminary action by pre-charging the bit line to a specific voltage level before the read operation begins. This pre-charging ensures that when the read operation is initiated, the bit line is already at the optimal voltage potential, eliminating the need for additional voltage adjustments during the read process and thereby reducing current flow while maintaining threshold voltage stability
Solution Approach 2:
The patent implements periodic action through staged voltage control of the select transistors. Different voltage levels are applied to the first and second select transistors at different time intervals during the read operation. This periodic voltage adjustment optimizes the read operation at each stage while minimizing overall current consumption by only applying necessary voltage control when needed
2Productivity
If peak current flow is reduced in the charge pump circuit, then device efficiency is improved, but voltage control complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the voltage control function into separate control mechanisms for the first and second select transistors. Each transistor receives independently controlled voltages from different control circuits, allowing optimized voltage profiles for each transistor without requiring complex centralized control, thereby reducing peak current flow while managing complexity through modular design
Solution Approach 2:
The patent introduces intermediary control circuits that mediate between the read operation requirements and the select transistor voltage needs. These intermediary circuits generate the appropriate voltage signals based on simple control inputs, reducing the complexity of direct voltage control while enabling efficient current management through intelligent voltage distribution
Data Source
AI summary
A semiconductor memory device comprises a bit line and source line, a first memory cell and first and second transistors connected therebetween, a second memory cell and third and fourth transistors connected therebetween, and first through fifth wirings connected to the first and the second memory cells and gate electrodes of the first to the fourth transistors. At a first timing of a read operation, voltages of the first through third wirings are larger than voltages of the fourth and fifth wirings. At a second timing, voltages of the second and third wirings are larger than voltages of the fourth and fifth wirings. At a third timing, voltages of the fourth and fifth wirings are larger than their voltages at the second timing. At a fourth timing, voltages of the second and third wirings are larger than a voltage of the fourth wiring.