L-Shaped Gate Semiconductor Device for Reduced Spacing
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Solution Overview
Problem
The challenge is to minimize the spacing between adjacent memory cells in semiconductor devices while maintaining adequate electrical isolation and allowing for the formation of electrical contacts, which is limited by the aspect ratio of the gates.
Innovation Solution
The solution involves forming an L-shaped second gate conductor with a low aspect ratio, achieved by creating an inter-gate dielectric structure and using a gate dielectric structure with alternating dielectric films, allowing for closer proximity of gates while ensuring proper electrical isolation through the use of dielectric layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If the aspect ratio of the gates is reduced to minimize spacing between adjacent memory cells, then the spacing between gates can be reduced, but the electrical isolation between gates and contacts becomes difficult to maintain
Solution Approach 1:
The patent introduces a vertical dimension by forming alternating dielectric films (first dielectric film and second dielectric film with different dielectric constants) stacked in the vertical direction. This multi-layer dielectric structure provides electrical isolation between gates and contacts while allowing horizontal spacing to be minimized, effectively resolving the contradiction by moving the isolation function to the vertical dimension rather than relying solely on horizontal spacing.
Solution Approach 2:
The patent uses composite dielectric structures consisting of multiple dielectric films with different dielectric constants (k-values). The first dielectric film has a first dielectric constant and the second dielectric film has a second dielectric constant, creating a composite material system that provides both electrical isolation and optimized capacitive coupling, enabling reduced gate spacing while maintaining isolation reliability.
2Area of stationary object
If the spacing between adjacent memory cells is minimized to reduce device physical size, then storage capacity per unit area increases, but adequate spacing for electrical contacts and electrical isolation becomes compromised
Solution Approach 1:
The patent resolves the manufacturing complexity issue by transitioning from two-dimensional lateral spacing to three-dimensional vertical stacking of dielectric films. This allows minimal lateral spacing between cells while maintaining adequate electrical isolation through the vertical dielectric layers, and provides sufficient space for contact formation without compromising isolation.
Solution Approach 2:
The patent segments the dielectric isolation function into multiple distinct layers (first dielectric film and second dielectric film) with different properties. This segmentation allows each layer to perform specific functions - one layer provides primary isolation while the other optimizes electrical characteristics - making the overall structure easier to manufacture with standard semiconductor processing techniques.
3Reliability
If alternating dielectric films with different dielectric constants are used in the gate dielectric structure, then electrical isolation is improved, but the device structure becomes more complex
Solution Approach 1:
The alternating dielectric film structure serves multiple functions simultaneously: the first dielectric film provides electrical isolation between gates and contacts, while the second dielectric film with different dielectric constant optimizes the capacitive coupling between gate and channel. This multi-functionality justifies the increased structural complexity by delivering superior electrical isolation and device performance.
Data Source
AI summary
A semiconductor device having a substrate, a dielectric layer over the substrate, a first gate conductor, an inter-gate dielectric structure and a second gate conductor is disclosed. A gate dielectric structure is disposed between the first gate conductor and the dielectric layer, and may include two or more dielectric films disposed in an alternating manner. The inter-gate dielectric structure may be disposed between the first gate conductor and the second gate conductor, and may include two or more dielectric films disposed in an alternating manner. The second gate conductor is formed in an L shape such that the second gate has a relatively low aspect ratio, which allows for a reduction in spacing between adjacent gates, while maintaining the required electrical isolation between the gates and contacts that may subsequently be formed.