Through-Silicon Via Layout for Uniform Current in Stacked Dies
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Solution Overview
Problem
As the number of stacked semiconductor dies increases, the current supply through through silicon vias (TSVs) becomes concentrated on certain vias, leading to reduced lifespan and increased risk of electromigration, particularly affecting vias adjacent to power-consuming circuits or in lower layers.
Innovation Solution
The semiconductor device distributes current uniformly through a group of through silicon vias, ensuring that each via carries an equivalent load, thereby preventing excessive current flow and reducing electromigration risks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of stacked semiconductor dies is increased, then the capacity of the memory device is improved, but the current concentration on certain through silicon vias increases leading to reduced lifespan and increased electromigration risk
Solution Approach 1:
The patent segments the current distribution by dividing the through silicon vias into multiple groups, where each group is electrically connected to a different power source terminal. This segmentation ensures that current is distributed across multiple vias rather than concentrated on fewer vias, thereby improving reliability and lifespan of the vias while maintaining the increased capacity from stacking more dies.
2Quantity of substance
If the number of through silicon vias providing supply voltage is increased, then the capacity of the memory device is improved, but the current flow through individual vias becomes excessive leading to electromigration
Solution Approach 1:
The patent segments the via groups into different electrical connections, where each group connects to a separate power source terminal. This segmentation strategy distributes the total current across multiple via groups, reducing the current density in individual vias and minimizing electromigration effects while maintaining the necessary voltage supply capacity.
Solution Approach 2:
The patent applies local quality by creating different electrical connection configurations for different groups of vias. Each via group has a specific electrical connection to a power source terminal, allowing localized current distribution that optimizes current density and reduces electromigration in specific via regions.
3Quantity of substance
If the number of through silicon vias is increased, then the capacity of the memory device is improved, but the current concentration on lower layer vias increases reducing their lifespan
Solution Approach 1:
The patent segments via groups into different electrical connections, ensuring that lower layer vias are distributed across multiple groups connected to different power source terminals. This segmentation prevents current concentration on lower layer vias, thereby extending their operational lifespan while supporting increased device capacity.
Solution Approach 2:
The patent implements local quality by creating differentiated electrical connection patterns for via groups at different locations and layers. This allows optimized current distribution that specifically protects lower layer vias from excessive current concentration, extending their lifespan while maintaining overall device performance.
Data Source
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AI summary
A semiconductor device includes first to M-th semiconductor dies stacked in a first direction. Each of the first to M-th semiconductor dies includes a substrate, first to K-th through silicon vias passing through the substrate in the first direction, and a first circuit to receive power through a power supply line electrically connected to the first through silicon via. Each of first to K-th through silicon vias of the N-th semiconductor die is electrically connected to a through silicon via of first to K-th through silicon vias of the (N+1)-th semiconductor die that is spaced apart therefrom in a plan view.