Dual Function Hybrid Memory Cell SONONS Architecture
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Solution Overview
Problem
Current memory devices either require frequent refresh cycles for dynamic random access memory (DRAM) or have long data retention but are expensive and power-consuming, necessitating a trade-off between size, cost, and functionality, as they cannot provide both DRAM and non-volatile memory (NVM) functionalities in a single cell.
Innovation Solution
A dual-function hybrid memory cell with two charge-trapping layers, where the bottom layer allows for quick charge storage with low voltage and short write time, and the top layer provides long data retention, enabling the cell to function as both DRAM and NVM, referred to as the Silicon-Oxide-Nitride-Oxide-Nitride-Silicon (SONONS) cell.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If DRAM memory cells are used to achieve high speed and low cost, then writing and reading speed is improved, but data retention deteriorates requiring frequent refresh cycles that consume large amounts of power
Solution Approach 1:
The memory cell is segmented into two distinct charge-trapping layers: a bottom charge-trapping layer for fast write operations (DRAM functionality) and a top charge-trapping layer for long-term data retention (NVM functionality). This segmentation allows each layer to optimize for its specific function, resolving the contradiction between speed and data retention.
Solution Approach 2:
The memory cell achieves multi-functionality by combining both DRAM and NVM capabilities in a single cell structure. The bottom charge-trapping layer provides fast write/read operations characteristic of DRAM, while the top charge-trapping layer provides long data retention characteristic of NVM, allowing the cell to serve multiple purposes simultaneously.
2Duration of action of moving object
If NVM memory devices are used to achieve long data retention without refresh cycles, then data retention is improved, but cost and power consumption worsen
Solution Approach 1:
The memory cell is segmented into two distinct charge-trapping layers: a bottom charge-trapping layer for fast write operations (DRAM functionality) and a top charge-trapping layer for long-term data retention (NVM functionality). This segmentation allows each layer to optimize for its specific function, resolving the contradiction between speed and data retention.
Solution Approach 2:
The memory cell achieves multi-functionality by combining both DRAM and NVM capabilities in a single cell structure. The bottom charge-trapping layer provides fast write/read operations characteristic of DRAM, while the top charge-trapping layer provides long data retention characteristic of NVM, allowing the cell to serve multiple purposes simultaneously.
3Adaptability or versatility
If multiple types of memory are used to obtain desired memory characteristics, then functionality is improved, but space and size requirements worsen
Solution Approach 1:
The patent merges DRAM and NVM functionalities into a single hybrid memory cell by stacking two charge-trapping layers vertically. This combining approach eliminates the need for separate DRAM and NVM memory blocks, significantly reducing the space requirements while maintaining both fast access and long-term retention capabilities.
Solution Approach 2:
The memory cell achieves multi-functionality by combining both DRAM and NVM capabilities in a single cell structure. The bottom charge-trapping layer provides fast write/read operations characteristic of DRAM, while the top charge-trapping layer provides long data retention characteristic of NVM, allowing the cell to serve multiple purposes simultaneously.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The SONONS cell reduces the size and cost of memory arrays by offering dual functionality, allowing for both short-term and long-term data storage with efficient power usage, addressing the limitations of standalone DRAM and NVM devices.
Implementation Method 1
The bottom charge-trapping layer is directly formed on top of the silicon or polysilicon channel. This allows electric charges to be stored in the bottom charge-trapping layer in a much shorter write time and using a lower write voltage.
Implementation Method 2
The top charge-trapping layer is isolated by dielectric layers and thus provides much longer data retention.
Data Source
AI summary
A dual function hybrid memory cell is disclosed. In one aspect, the memory cell includes a substrate, a bottom charge-trapping region formed on the substrate, a top charge-trapping region formed on the bottom charge-trapping region, and a gate layer formed on the top charge trapping region. In another aspect, a method for programming a memory cell having a substrate, a bottom charge-trapping layer, a top charge-trapping layer, and a gate layer is disclosed. The method includes biasing a channel region of the substrate, applying a first voltage differential between the gate layer and the channel region, injecting charge into the bottom charge-trapping layer from the channel region based on the first voltage differential. The method also includes applying a second voltage differential between the gate layer and the channel region and injecting charge from the bottom charge-trapping layer into the top charge-trapping layer based on the second voltage differential.