Bonded Processor-SRAM Stack for Low-RC Cache Interconnects
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Solution Overview
Problem
Modern microprocessors face performance degradation due to significant resistive-capacitive (RC) delays from cache to processor core, as cache size increases and interconnect distances become substantial, affecting both performance and yield.
Innovation Solution
A semiconductor device with a processor and static random-access memory (SRAM) cache integrated on a bonded chip, utilizing short-distance vertical metal interconnects instead of long-distance routing, reducing interconnect distance from centimeter-level to micrometer-level and enhancing data transfer speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If cache size is increased to enhance processor performance, then memory capacity is improved, but resistive-capacitive delay increases due to longer interconnect distances
Solution Approach 1:
The patent transitions from planar (2D) cache organization to three-dimensional (3D) stacked architecture, where SRAM cache is bonded vertically above the processor. This dimensional change enables much shorter vertical interconnect distances compared to horizontal routing, reducing RC delay while maintaining large cache capacity. The 3D integration allows cache cells to be positioned micrometers above processor cores rather than centimeters away in planar layouts.
Solution Approach 2:
The patent implements nested integration by placing the SRAM cache array directly above the processor core, with bonding contacts penetrating through the cache structure to connect to processor interconnects. This nesting arrangement allows the cache to be positioned as close as possible to the processing elements, minimizing interconnect distance and RC delay while maximizing cache density.
2Quantity of substance
If cache size is increased to enhance processor performance, then memory capacity is improved, but chip size increases
Solution Approach 1:
By stacking the SRAM cache array vertically above the processor using 3D integration, the patent utilizes the third dimension to increase cache capacity without proportionally increasing the lateral chip footprint. This vertical stacking allows large cache sizes to be achieved within a compact planar area, significantly improving cache density compared to traditional 2D layouts.
3Productivity
If wafer-level bonding is used to integrate processor and SRAM, then manufacturing efficiency is improved, but alignment precision must be maintained across large wafer areas
Solution Approach 1:
The patent incorporates alignment marks and reference structures during the separate fabrication of processor and SRAM wafers before bonding. These preliminary features enable precise alignment to be established and maintained across the entire wafer area during the wafer-level bonding process, ensuring accurate interconnect registration without requiring post-bonding adjustment.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration significantly reduces RC delay, minimizes chip size, and increases data transfer speed while shortening manufacturing cycles and improving yield through hybrid bonding.
Implementation Method 1
The first wafer and the second wafer are bonded in a face-to-face manner, such that the at least one of the first semiconductor structures is bonded to the at least one of the second semiconductor structures
Data Source
AI summary
Embodiments of semiconductor devices and fabrication methods thereof are disclosed. In an example, a semiconductor device includes a first semiconductor structure including a device layer, a first interconnect layer, and a first bonding layer. The device layer includes a processor and a logic circuit, and the first bonding layer includes a first bonding contact. The semiconductor device also includes a second semiconductor structure including an array of static random-access memory (SRAM) cells, a second interconnect layer, and a second bonding layer including a second bonding contact. The first bonding contact is in contact with the second bonding contact. The processor is electrically connected to the array of SRAM cells through the first interconnect layer, the first bonding contact, the second bonding contact, and the second interconnect layer. The logic circuit is electrically connected to the array of SRAM cells through the first interconnect layer, the first bonding contact, the second bonding contact, and the second interconnect layer.