Lateral Electrostatic Protection Element With Emitter-Base Clearance

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Solution Overview

Problem

Conventional BJT-type electrostatic protective elements face limitations in setting high snapback voltage due to impurity concentration and thickness constraints, leading to inadequate protection for high withstand voltage circuits, and risk of short-circuiting between collector and base regions.

Innovation Solution

The design includes a first and second impurity region of different conductivity types on a semiconductor substrate, with a collector contact, base contact, and emitter contact, where the emitter contact is positioned closer to the collector contact than the base contact, forming a clearance to prevent short-circuiting and allow for adjustable snapback voltage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If impurity regions are lined up in longitudinal direction with limited thickness, then device size is reduced, but snapback voltage cannot be set high enough for high withstand voltage circuits

Engineering Contradiction:
Improvedevice sizeVSAvoidsnapback voltage level
Core Design Contradiction:
Volume of moving objectVSReliability

Solution Approach 1:

The patent transitions from a longitudinal arrangement (depth direction) to a lateral arrangement (horizontal direction) of impurity regions. This dimensional change allows the collector and base regions to be separated by a larger distance while maintaining a compact device footprint, enabling high snapback voltage without increasing device size.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent changes the separation distance parameter between collector and base regions by arranging them laterally rather than longitudinally. This parameter change enables the snapback voltage to be set at high levels (100V or more) while keeping the device size small, resolving the contradiction between size reduction and voltage level.

Inventive Principle:
Principle #35Parameter changes

2Ease of manufacture

If P-well concentration is high in lateral structure, then manufacturing is simplified, but snapback voltage cannot be controlled according to separation distance and short-circuit risk increases

Engineering Contradiction:
Improvemanufacturing simplicityVSAvoidsnapback voltage control and short-circuit prevention
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent applies different impurity concentrations to different regions: the collector region has a first concentration, the base region has a second concentration, and the P-well has a third concentration that is lower than both. This local differentiation allows precise control of snapback voltage through the separation distance while preventing short-circuits, even though manufacturing becomes slightly more complex.

Inventive Principle:
Principle #3Local quality

3Volume of moving object

If collector and base are adjacent in lateral structure, then device size is reduced, but short-circuit risk between collector and base increases

Engineering Contradiction:
Improvedevice sizeVSAvoidshort-circuit risk
Core Design Contradiction:
Volume of moving objectVSObject-affected harmful factors

Solution Approach 1:

The patent introduces a P-well region as an intermediary between the collector and base regions. This P-well acts as a protective barrier that prevents direct contact between the n-type collector and base regions, eliminating the short-circuit risk while allowing the device to maintain a compact lateral structure.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration enhances protective performance against static electricity, allows for higher snapback voltage, and reduces manufacturing complexity by eliminating the need for a trench between collector and base contacts, enabling better protection for high withstand voltage circuits.

Implementation Method 1

a first impurity region of a first conductivity type which is formed on a predetermined surface side of a semiconductor substrate; a second impurity region of a second conductivity type which is formed on the predetermined surface side of the semiconductor substrate so as to form a clearance in a horizontal direction with respect to the first impurity region

Methodology Applied
Scientific EffectElectrical isolation through impurity regions: Electrical Resistance

Implementation Method 2

a collector contact which is formed on a predetermined surface side in the first impurity region, which has a higher concentration than the first impurity region, and which is an impurity region of the first conductivity type; a base contact which is formed on a predetermined surface side in the second impurity region, which has a higher concentration than the second impurity region, and which is an impurity region of the second conductivity type; and an emitter contact which is formed on a predetermined surface side in the second impurity region at a position that is closer to the collector contact than the base contact

Methodology Applied
Scientific EffectBipolar transistor operation: Avalanche Breakdown

Data Source

PatentUS11581301B2Electrostatic protective element and electronic device
Publication Date: 2023.02.14 SONY GROUP CORP
  • US11581301B2 patent drawing
  • US11581301B2 patent drawing
  • US11581301B2 patent drawing

AI summary

The present technique relates to an electrostatic protective element that enables protective performance with respect to static electricity to be improved and to an electronic device. An electrostatic protective element includes: a first impurity region of a first conductivity type which is formed on the predetermined surface side of a semiconductor substrate; a second impurity region of a second conductivity type which is formed on the predetermined surface side of the semiconductor substrate so as to form a clearance in a horizontal direction with respect to the first impurity region; a collector contact which is formed on the predetermined surface side in the first impurity region, which has a higher concentration than the first impurity region, and which is an impurity region of the first conductivity type; a base contact which is formed on the predetermined surface side in the second impurity region, which has a higher concentration than the second impurity region, and which is an impurity region of the second conductivity type; and an emitter contact which is formed on the predetermined surface side in the second impurity region at a position that is closer to the collector contact than the base contact, which has a higher concentration than the second impurity region, and which is an impurity region of the first conductivity type. The present technique can be applied to, for example, an electronic device.