Driving Transistor Gate Insulation Layout for High-Voltage Displays
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Solution Overview
Problem
Display devices, such as LCDs and OLEDs, face challenges in maintaining stable operation of driving transistors in the driving circuit portion when subjected to high voltages, leading to on-current deterioration and threshold voltage shifts, which affects the reliability and stability of the driving circuit.
Innovation Solution
The design includes a driving circuit portion with a specific gate insulation layer structure, where the outer portion of the gate insulation layer does not overlap the gate electrode, and has a wider width in one direction, which helps in preventing a strong electric field formation between the drain region and the gate electrode, thereby maintaining on-current and threshold voltage stability even under high voltage conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional gate insulation layer structure is used, then the device structure is simple, but the driving transistor deteriorates under high voltage conditions
Solution Approach 1:
The gate insulation layer is divided into multiple distinct layers (first gate insulation layer and second gate insulation layer) with different widths. The first gate insulation layer has a wider width than the second gate insulation layer, creating a stepped structure that segments the insulation function across different regions to prevent strong electric field formation while maintaining overall structural integrity.
Solution Approach 2:
Different regions of the gate insulation structure are given different properties - the first gate insulation layer has a larger width in the first direction to provide enhanced insulation where needed, while the second gate insulation layer has a smaller width to maintain proper electrical characteristics in other regions. This local differentiation allows the structure to simultaneously prevent electric field concentration and maintain transistor functionality.
2Object-affected harmful factors
If the gate insulation layer outer portion overlaps the gate electrode, then the insulation is more complete, but a strong electric field forms between drain region and gate electrode
Solution Approach 1:
The outer portion of the first gate insulation layer is intentionally designed to not overlap with the gate electrode in the first direction, effectively removing the overlapping region that would create a strong electric field between the drain region and gate electrode. This extraction of the problematic overlapping portion eliminates the source of electric field concentration while the insulation function is maintained through the extended width of the first gate insulation layer in other regions.
3Adaptability or versatility
If the driving circuit operates under high voltage, then the voltage range is expanded, but on-current deterioration occurs
Solution Approach 1:
The stepped gate insulation layer structure is designed in advance to prevent strong electric field formation before high voltage is applied. By creating the wider first gate insulation layer that extends beyond the gate electrode boundaries, the structure provides pre-established protection against electric field concentration, cushioning the transistor against voltage stress before it occurs and preventing on-current deterioration during high voltage operation.
Data Source
AI summary
A display device includes pixel circuits disposed in a display area and a driving circuit disposed in the peripheral area. The driving circuit includes a first transistor and each pixel circuit includes a second transistor. The first transistor includes a first active pattern disposed on the substrate, a first gate insulation layer having a first outer portion disposed on the first active pattern, and a first gate electrode disposed on the first gate insulation layer. The second transistor includes a second active pattern disposed on the substrate, a second gate insulation layer having a second outer portion disposed on the second active pattern, and a second gate electrode disposed on the second gate insulation layer. The first outer portion doesn't overlap the first gate electrode and has a first width. The second outer portion doesn't overlap the second gate electrode and has a second width smaller than the first width.