Power MOSFET Gate Structure for Lower On-Resistance
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Solution Overview
Problem
Power MOSFETs face challenges with high on-resistance and overlay control issues, which affect their performance and efficiency in switching and amplification tasks.
Innovation Solution
The design includes a substrate with specific doping regions, a field plate, and a fully covered gate electrode by a silicide layer to reduce gate resistance and improve overlay control, along with spacers to prevent ion diffusion, resulting in enhanced breakdown voltage and on-resistance performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional power MOSFET structure is used, then device simplicity is maintained, but high on-resistance and overlay control problems occur
Solution Approach 1:
The gate electrode is divided into multiple segments with different silicide layer configurations. The first gate electrode portion has a first silicide layer while the second gate electrode portion has a second silicide layer, allowing independent optimization of each segment for overlay control and electrical performance
Solution Approach 2:
Different regions of the gate electrode are given different properties through selective silicide layer formation. The first portion receives a silicide layer with specific characteristics while the second portion receives a different silicide layer, creating local quality variations that address overlay control in critical areas without compromising overall device performance
2Loss of energy
If gate electrode is not fully covered by silicide layer, then manufacturing is simpler, but gate resistance is high causing increased switching loss
Solution Approach 1:
The gate electrode is segmented into multiple portions with different silicide coverage. The first gate electrode portion is fully covered by a first silicide layer to minimize resistance, while the second gate electrode portion has a second silicide layer that may be partially covering, allowing optimization of switching loss without requiring complete silicide coverage of the entire gate structure
Solution Approach 2:
The silicide layer coverage and thickness are varied across different gate electrode portions. By changing the coverage parameter from full coverage in the first portion to partial or different coverage in the second portion, the patent optimizes the balance between gate resistance reduction and manufacturing complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration significantly reduces gate resistance, improves switching loss and dead time, and enhances the overall performance of the power MOSFET by aligning it closer to the silicon limit, offering better efficiency and circuit performance compared to conventional power MOSFETs.
Implementation Method 1
a fully covered gate electrode by a silicide layer to reduce gate resistance
Implementation Method 2
a substrate with specific doping regions
Implementation Method 3
spacers to prevent ion diffusion
Data Source
AI summary
A semiconductor device is provided. The semiconductor device includes a substrate, a field plate, a gate electrode, and a first dielectric layer. The substrate has a top surface. The substrate includes a first drift region with a first conductivity type extending from the top surface of the substrate into the substrate, and includes a second drill region with the first conductivity type extending from the top surface of the substrate into the substrate and adjacent to the first drift region. The field plate is over the substrate. The gate electrode has a first portion and a second portion, wherein the first portion of the gate electrode is located over the field plate. The first dielectric layer is between the substrate and the field plate. The first portion of the gate electrode is overlapping with a boundary of the first drift region and the second drift region in the substrate.