SOI FET with Epitaxial Source and Drain Regions
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Solution Overview
Problem
Semiconductor-on-insulator (SOI) field effect transistors face challenges in forming metal semiconductor alloy materials due to the thinness of the semiconductor layer, leading to increased Miller capacitance with raised source and drain regions and higher on-resistance with polycrystalline regions.
Innovation Solution
A semiconductor structure is formed with a semiconductor channel portion, gate dielectric, and gate electrode on an insulator layer, enclosed by a dielectric spacer, and undercut using an isotropic etch, allowing for epitaxial deposition of source and drain regions that are in contact with the channel, enabling the formation of metal semiconductor alloy portions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If raised source and drain regions are formed to enable metal semiconductor alloy materials, then the formation of metal alloys becomes possible, but Miller capacitance increases
Solution Approach 1:
The source and drain regions are formed in a lateral dimension rather than vertically raising them. The epitaxial source and drain regions extend laterally from the channel region, allowing metal alloy formation without vertical elevation that would increase Miller capacitance between gate and source/drain.
Solution Approach 2:
Epitaxial growth is applied locally to specific regions where source and drain contacts are needed. The epitaxial source and drain regions are formed only in the contact areas, providing suitable material quality for metal alloy formation while maintaining the original thin channel thickness elsewhere to minimize capacitance.
2Ease of manufacture
If polycrystalline source and drain regions are used, then source and drain regions can be formed, but on-resistance increases due to grain boundaries
Solution Approach 1:
The crystal structure parameter is changed from polycrystalline to epitaxial (single-crystal-like) growth. The epitaxial source and drain regions are grown with controlled crystal orientation, eliminating grain boundaries that would increase resistance while still allowing formation of these regions in the SOI structure.
3Length of moving object
If the semiconductor layer thickness is reduced to 2-30 nm for ETSOI devices, then device scaling is achieved, but metal semiconductor alloy formation becomes insufficient
Solution Approach 1:
Epitaxial source and drain regions are formed in advance before final metal alloy formation. These pre-formed epitaxial regions provide a suitable substrate and structural foundation that enables subsequent metal semiconductor alloy formation even in the thin 2-30 nm ETSOI layer, where direct alloy formation would be insufficient.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces Miller capacitance and on-resistance by using epitaxially grown source and drain regions, improving the performance of SOI field effect transistors while allowing for the formation of metal semiconductor alloy materials.
Implementation Method 1
The material stack and the dielectric spacer are undercut by an isotropic etch that removes the material of the insulator layer selective to the material of the dielectric spacer
Implementation Method 2
A selective epitaxy process is employed to deposit a doped semiconductor material, which forms a source region and a drain region that are epitaxially in contact with the semiconductor channel portion
Data Source
AI summary
A material stack including a semiconductor channel portion, a gate dielectric, a gate electrode, and a gate cap dielectric portion is formed on an insulator layer. The material stack is laterally enclosed by a dielectric spacer including a dielectric material that is different from the dielectric material of the insulator layer. The material stack and the dielectric spacer are undercut by an isotropic etch that removes the material of the insulator layer selective to the material of the dielectric spacer. A selective epitaxy process is employed to deposit a doped semiconductor material, which forms a source region and a drain region that are epitaxially in contact with the semiconductor channel portion. Metal semiconductor alloy portions can be formed on the source region and the drain region.