Semiconductor Memory Cell Transistor Segmentation for Area-Speed Trade-off
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Solution Overview
Problem
Semiconductor memory devices face a trade-off between manufacturing variations and operating speed, where increasing the gate width of cell transistors to reduce variations leads to increased circuit area, and vice versa, affecting the balance between current flow and data reading speed.
Innovation Solution
The semiconductor memory device employs a three bit line-type memory cell configuration, where the gate width of the cell transistor is increased by three times, allowing for improved reading speed while maintaining the same circuit area and storage capacity, by using a memory cell array with a word line, bit lines, and a read circuit with an encoding circuit to manage the connection states of the cell transistor and bit lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate width of the cell transistor is increased to reduce manufacturing variation and increase current flow, then the operating speed and current flow are improved, but the circuit area is increased
Solution Approach 1:
The patent divides the bit line into multiple segments (first bit line and second bit line) and uses multiple cell transistors (first and second cell transistors) to control different segments. This segmentation allows the total gate width to be distributed across multiple transistors, achieving the required current flow and speed performance without concentrating all the gate width in a single transistor, thus avoiding excessive circuit area occupation by any single cell structure.
2Speed
If the gate width of the cell transistor is increased to increase current flow for high-speed data reading, then the reading speed is improved, but the circuit area is increased
Solution Approach 1:
The bit line is segmented into multiple sections controlled by different cell transistors. The first cell transistor controls the first bit line segment and the second cell transistor controls the second bit line segment. This segmentation enables high-speed reading by distributing the current flow requirement across multiple transistors with moderate gate widths, achieving the same total current capability without requiring a single oversized transistor that would occupy excessive area.
Solution Approach 2:
The patent introduces a new dimension to the circuit architecture by adding multiple bit line segments and corresponding control transistors. Instead of increasing the gate width of a single transistor in one dimension, the solution expands the circuit structure into multiple parallel paths (different bit line segments), achieving high current flow and reading speed through spatial distribution rather than single-component scaling.
3Area of stationary object
If the gate width of the cell transistor is decreased to reduce circuit area, then the circuit area is reduced, but the manufacturing variation and operating speed are degraded
Solution Approach 1:
By segmenting the bit line and using multiple cell transistors, each transistor can have a smaller gate width that fits within acceptable manufacturing variation tolerances. The combined effect of multiple transistors with moderate gate widths achieves the same total current capability as a single large transistor, thereby reducing sensitivity to manufacturing variations while maintaining small circuit area.
4Area of stationary object
If the gate width of the cell transistor is decreased to reduce circuit area, then the circuit area is reduced, but the current flow and reading speed are degraded
Solution Approach 1:
The bit line is divided into multiple segments controlled by separate cell transistors. Each transistor operates independently to drive its assigned bit line segment, allowing the system to achieve high total current flow through parallel operation of multiple transistors with smaller gate widths, thus maintaining high reading speed while reducing the area occupied by each individual cell transistor.
Data Source
AI summary
A semiconductor memory device according to an embodiment includes a memory cell array including memory cells each formed from a transistor formed over an active area of a well and disposed at intersections of a word line and a bit line group, the memory cell having different connection states including a state in which a source or a drain of the transistor is not electrically connected to any one of bit lines belonging to the bit line group and states in which the source or the drain is electrically connected only to a specific one of the bit lines, and an active area serving as a gate of the transistor being continuously formed in arrangement areas of the bit lines of the bit line group and spaces between the bit lines.