3D Vertical NAND Gate Stacking for Memory Area Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge is to reduce the size of highly integrated memory devices while minimizing the impact of increasing operation circuits and wiring structures, which hinder the miniaturization of memory devices.
Innovation Solution
A non-volatile memory device design featuring a substrate with a peripheral circuit, a memory cell array, and a second gate structure electrically isolated from the memory cell array, allowing for a reduced layout area and smaller semiconductor chip size by using a 3D memory array with vertical NAND strings and a second gate structure as a circuit element or test element.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell size is reduced to increase capacity, then storage capacity is improved, but operation circuits and wiring structures occupy more area preventing device miniaturization
Solution Approach 1:
The patent transitions from planar 2D memory cell arrangement to 3D vertical stacking architecture. Multiple gate electrodes are stacked in the perpendicular direction to form a three-dimensional structure, enabling memory cells to be arranged in the vertical dimension. This dimensional change allows increased storage capacity without proportionally increasing the planar footprint, effectively resolving the contradiction between capacity and device area.
Solution Approach 2:
The patent implements a nested structure where vertical channel structures penetrate through multiple stacked gate electrodes. The channel structures are positioned within the vertical stack of gate electrodes, creating a compact nested arrangement. This nesting enables multiple memory cells to share common structures vertically, increasing capacity while minimizing the area occupied by operation circuits and wiring.
2Adaptability or versatility
If more operation circuits and wiring structures are added for high integration, then functionality is improved, but device size increases
Solution Approach 1:
The patent designs the vertical channel structures to serve multiple functions: they act as conductive paths for memory cells, provide structural support for the stacked gate electrodes, and enable electrical connectivity across multiple memory layers. This multi-functionality reduces the need for separate dedicated structures, allowing enhanced functionality without proportional area increase.
Solution Approach 2:
The patent merges multiple functional elements into a unified vertical stack structure. Gate electrodes, channel structures, and insulating layers are combined into an integrated three-dimensional memory cell array. This merging consolidates what would traditionally require separate planar components into a compact vertical assembly, improving functionality while minimizing device area.
Data Source
AI summary
A non-volatile memory device is provided as follows. A substrate has a peripheral circuit. A first semiconductor layer is disposed on the substrate. The first semiconductor layer includes a memory cell region. A first gate structure is disposed on the first semiconductor layer. The first gate structure includes a plurality of first gate electrodes stacked in a perpendicular direction to the first semiconductor layer and a plurality of vertical channel structures penetrating the plurality of first gate electrodes. The first gate structure is arranged in the memory cell region. A second gate structure is disposed on the substrate. The second gate structure includes a plurality of second gate electrodes stacked in the perpendicular direction to the first semiconductor layer. The second gate structure is arranged outside the memory cell region.