Memory Element Spacer Structure for Metal Residue Confinement

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Solution Overview

Problem

The formation of memory elements like ReRAM can result in metallic residues that interfere with other circuitry, posing a challenge in implementing logic or other functions within the same device.

Innovation Solution

A structure and method are provided to confine metal residues within a spacer, ensuring they are not present in areas where they could interfere with other components, by forming a memory element over an insulator layer with a spacer adjacent to its sidewall and a metal-dielectric layer between the spacer and the insulator, allowing the metal to be removed from non-memory element portions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If memory elements are formed using conventional methods, then memory elements can be created, but metallic residues are produced that interfere with other circuitry

Engineering Contradiction:
Improvememory element formationVSAvoidmetallic residue interference
Core Design Contradiction:
Ease of manufactureVSObject-generated harmful factors

Solution Approach 1:

The patent extracts and removes metallic residues from areas where they would interfere with circuitry by selectively etching metal layers only in specific regions defined by spacer structures, while preserving metal in memory element regions

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent introduces spacer structures as intermediary elements that act as masks during etching processes, controlling where metal is removed and where it is retained, thereby mediating between metal layer formation and interference prevention

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If metal is removed to prevent interference, then circuit functionality is improved, but memory element formation becomes more complex

Engineering Contradiction:
Improvecircuit functionalityVSAvoidmemory element formation process
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent performs preliminary actions by forming spacer structures and defining etch masks before completing metal layer formation, allowing selective removal of metal in advance while preserving it in memory element regions, thereby simplifying subsequent processing

Inventive Principle:
Principle #10Preliminary action

3Object-generated harmful factors

If spacers are used to confine metal, then metal interference is prevented, but device structure becomes more complex

Engineering Contradiction:
Improvemetal interferenceVSAvoidstructure complexity
Core Design Contradiction:
Object-generated harmful factorsVSDevice complexity

Solution Approach 1:

The patent makes the spacer structures multi-functional by using them simultaneously as etch masks for selective metal removal, as physical barriers to confine metal residues, and as structural components that define device regions, thereby preventing metal interference without proportionally increasing complexity

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS20240130255A1Structure and method for memory element to confine metal with spacer
Publication Date: 2024.04.18 GLOBALFOUNDRIES US INC
  • US20240130255A1 patent drawing
  • US20240130255A1 patent drawing
  • US20240130255A1 patent drawing

AI summary

The disclosure provides a structure and method for a memory element to confine a metal (e.g., a remaining portion of a metallic residue) with a spacer. A structure according to the disclosure includes a memory element over a first portion of an insulator layer. A portion of the memory element includes a sidewall over the insulator layer. A spacer is adjacent the sidewall of the memory element and on the first portion of the insulator layer. A metal-dielectric layer is within an interface between the spacer and the sidewall or an interface between the spacer and the first portion of the insulator layer. The insulator layer includes a second portion adjacent the first portion, and the second portion does not include the memory element, the spacer, and the metal-dielectric layer thereon.