Chip Package TSV Isolation Structure for Higher Pad Density

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Solution Overview

Problem

The challenge in chip packaging is to reduce conductive pad pitch without increasing the chip package size, which complicates the fabrication process and reduces yield, especially for high-performance semiconductor chips with multiple I/O pins.

Innovation Solution

A chip package design featuring a substrate with first and second openings, an electrical isolation structure, and a conductive structure that includes through substrate vias (TSVs) to increase the number of conductive pads and improve design flexibility, while reducing the passivation layer coverage and stress-induced issues.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the conductive pad pitch is reduced to increase the number of I/O pins, then the number of conductive pads increases, but the fabrication process becomes more complex and yield decreases

Engineering Contradiction:

Improvenumber of conductive padsVSAvoidfabrication process complexity

Core Design Contradiction:

Quantity of substanceVSDevice complexity

Solution Approach 1:

The substrate is divided into multiple regions with different opening configurations. First openings are surrounded by second openings, creating distinct zones for different conductive structures. This segmentation allows simultaneous fabrication of multiple pad types without increasing overall process complexity

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Second openings are nested around first openings, creating a concentric structure where the larger second opening surrounds the smaller first opening. This nested configuration allows two conductive structures to share the same substrate region, effectively doubling the pad density without proportionally increasing fabrication steps

Inventive Principle:

Principle #7Nested doll (Nesting)

2Quantity of substance

If the conductive pad pitch is reduced to increase the number of I/O pins, then the number of conductive pads increases, but the yield of chip packages decreases

Engineering Contradiction:

Improvenumber of conductive padsVSAvoidchip package yield

Core Design Contradiction:

Quantity of substanceVSReliability

Solution Approach 1:

Electrical isolation structures are formed beforehand to prevent stress propagation between adjacent conductive pads. The isolation structures are positioned to cushion against stress-induced failures, protecting the overall package yield even as pad density increases

Inventive Principle:

Principle #11Beforehand cushioning (Prior cushioning)

Solution Approach 2:

Different regions of the substrate have different opening configurations - first openings for one type of conductive structure and second surrounding openings for another type. This local differentiation allows optimization of each region's electrical and mechanical properties independently, maintaining high yield across the entire package

Inventive Principle:

Principle #3Local quality

3Quantity of substance

If through substrate vias are used to increase conductive pads, then the number of pads increases, but stress-induced issues and passivation layer coverage problems arise

Engineering Contradiction:

Improvenumber of conductive padsVSAvoidstress-induced issues

Core Design Contradiction:

Quantity of substanceVSObject-affected harmful factors

Solution Approach 1:

Electrical isolation structures serve as intermediary elements between adjacent conductive pads and between conductive pads and the substrate. These isolation structures mediate stress distribution, preventing stress-induced failures while allowing the increased pad density provided by through substrate vias

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The electrical isolation structures extract and contain stress within localized regions, preventing stress propagation to adjacent sensitive structures. By taking out the stress concentration problem and isolating it within the isolation structure regions, the overall reliability of the high-density pad array is maintained

Inventive Principle:

Principle #2Taking out (Extraction)

Data Source

PatentUS11973095B2Method for forming chip package with second opening surrounding first opening having conductive structure therein

Publication Date: 2024.04.30 XINTEC INC

AI summary

A chip package including a substrate, a first conductive structure, and an electrical isolation structure is provided. The substrate has a first surface and a second surface opposite the first surface), and includes a first opening and a second opening surrounding the first opening. The substrate includes a sensor device adjacent to the first surface. A first conductive structure includes a first conductive portion in the first opening of the substrate, and a second conductive portion over the second surface of the substrate. An electrical isolation structure includes a first isolation portion in the second opening of the substrate, and a second isolation portion extending from the first isolation portion and between the second surface of the substrate and the second conductive portion. The first isolation portion surrounds the first conductive portion.