HBM Cap Substrate Thickness for Warpage-Matched Die Stacks
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Solution Overview
Problem
High-bandwidth memory (HBM) stacks face challenges in maintaining reliable electrical connections due to warpage differences between the cap substrate and memory dies, leading to voids and potential electrical connection failures, especially as the number of stacked dies increases.
Innovation Solution
The implementation of a cap substrate with a thickness ranging from 50 μm to 80 μm, adjusted to match the warpage value of the topmost memory die, and bonding interfaces using metal-to-metal and dielectric-to-dielectric bonding techniques to ensure void-free interfaces and secure electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of stacked memory dies is increased to enhance memory capacity, then the memory capacity is improved, but the warpage difference between the cap substrate and memory dies increases, leading to voids and electrical connection failures
Solution Approach 1:
The patent adjusts the thickness of the cap substrate as a physical parameter to match the warpage characteristics of the stacked memory dies. By changing the thickness parameter within a specific range (50-80 μm), the cap substrate's warpage is optimized to be substantially equal to that of the memory dies, ensuring reliable electrical connections while supporting high memory capacity configurations
Solution Approach 2:
The patent preemptively compensates for warpage-induced voids by pre-adjusting the cap substrate thickness before bonding. This prior cushioning approach ensures that the bonding interface is free from voids that would otherwise form due to warpage differences, preventing electrical connection failures before they occur
2Reliability
If the cap substrate thickness is reduced to minimize warpage difference, then the warpage matching is improved, but the structural support and mechanical strength are compromised
Solution Approach 1:
The patent identifies and optimizes the cap substrate thickness parameter within a specific range (50-80 μm) that simultaneously satisfies both warpage matching requirements and structural support needs. This parameter optimization ensures that the cap substrate is thin enough to match warpage but thick enough to provide adequate mechanical strength
Solution Approach 2:
Rather than making the cap substrate extremely thin to achieve perfect warpage matching, the patent uses a partially optimized thickness that provides sufficient warpage matching while maintaining adequate structural support. This partial action approach avoids the excessive thinning that would compromise mechanical strength
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces warpage-induced voids and enhances the reliability of electrical connections between memory dies and the cap substrate, maintaining the integrity of the HBM stack even with multiple stacked layers.
Implementation Method 1
bonding interfaces using metal-to-metal and dielectric-to-dielectric bonding techniques
Implementation Method 2
bonding interfaces using metal-to-metal and dielectric-to-dielectric bonding techniques
Data Source
AI summary
Provided are a semiconductor device and a method for manufacturing the same, and a semiconductor package. The semiconductor device includes a die stack and a cap substrate. The die stack includes a first die, second dies stacked on the first die, and a third die stacked on the second dies. The first die includes first through semiconductor vias. Each of the second dies include second through semiconductor vias. The third die includes third through semiconductor vias. The cap substrate is disposed on the third die of the die stack. A sum of a thickness of the third die and a thickness of the cap substrate ranges from about 50 μm to about 80 μm.