3D Memory Device Fabrication via Stacked Trench and Recess Architecture
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current 3D memory devices, such as NOR-type cross-point arrays, face limitations in scaling capability, memory density, high programming current, and non-linear resistor devices, making them inefficient for neuromorphic computing and machine learning applications.
Innovation Solution
A 3D memory device with a multi-layer stacking structure, including conductive and insulating layers, trench, and recess regions, featuring a dielectric blocking strip, floating gates, and a semiconductor strip with doping regions, which allows for improved memory cell design and twisted layout to prevent sneak paths during programming.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If 1T1R structure is used in cross-point array, then sum-of-products function can be realized, but memory density is limited below 1 Gb
Solution Approach 1:
The patent transitions from planar 2D cross-point array to vertical 3D stacked architecture, stacking multiple memory layers along the vertical direction to achieve high memory density while maintaining cross-point array functionality for sum-of-products operations
Solution Approach 2:
The patent implements nested structure by placing control gates, bit lines, and source lines in overlapping vertical positions across multiple stacked layers, with each layer containing complete memory cell structures that are vertically integrated to maximize space utilization
2Use of energy by moving object
If ReRAM or PCM is used with 1T1R structure, then memory function is achieved, but programming current is high (>50 uA per cell)
Solution Approach 1:
The patent segments the programming operation across multiple stacked layers, where each layer contributes a portion of the total programming current, distributing the current burden and enabling highly parallel programming with reduced per-cell current requirements
Solution Approach 2:
The patent merges multiple memory layers into a unified 3D structure that operates collectively for programming operations, combining the computational power of multiple layers to achieve efficient parallel programming with lower overall current consumption
3Reliability
If ReRAM or PCRAM resistor devices are used, then memory storage is achieved, but devices are highly non-linear with respect to applied bias
Solution Approach 1:
The patent modifies the electrical characteristics of memory cells through controlled doping regions and multi-layer configurations, adjusting resistance parameters to achieve more linear voltage-current relationships that facilitate analog computing operations
4Quantity of substance
If multi-layer stacking structure is implemented, then memory density is enhanced, but fabrication complexity increases
Solution Approach 1:
The patent employs preliminary patterning and alignment procedures during fabrication, pre-positioning conductive layers, insulating layers, and semiconductor strips in precise staggered arrangements before final assembly, simplifying the multi-layer stacking process
Solution Approach 2:
The patent designs universal fabrication processes and structures that can be replicated across multiple stacked layers, using standardized conductive layers, insulating layers, and semiconductor strip configurations that reduce fabrication complexity through reusability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances memory density, reduces programming current, and improves retention reliability, enabling more efficient sum-of-products operations and increased bandwidth in neuromorphic computing systems.
Implementation Method 1
The dielectric blocking strip is disposed in the trench and the recess regions to at least partially overlapping the plurality of conductive layers. Each of the floating gates is disposed in one of the recess regions and isolated from the conductive layers by the dielectric blocking strip.
Implementation Method 2
The dielectric strip comprising silicon oxide is disposed in the trench and overlies sidewalls of the floating gates that are exposed from the recess regions. The semiconductor strip is disposed in the trench, insulated from the floating gates by the dielectric strip.
Implementation Method 3
The semiconductor strip is disposed in the trench, insulated from the floating gates by the dielectric strip, and includes a first doping region, a second doping region and a channel region, wherein both is of the first doping region and the second doping region are disposed adjacent to the floating gates, and the channel region is disposed between and connects to the first doping region and the second doping region.
Data Source
AI summary
A 3D memory device includes a multi-layers stacking structure having a plurality of conductive layers and insulating layers stacked in a staggered manner, at least one trench passing through the conductive layers and a plurality of recess regions extending into the conductive layers from the trench; a dielectric blocking strip lining sidewalls of the trench and the recess regions; a plurality of floating gates disposed in the recess regions and isolated from the conductive layers by the dielectric blocking strip; a dielectric strip overlies sidewalls of the floating gates exposed from the recess regions; a semiconductor strip disposed in the trench, insulated from the floating gates by the dielectric strip, and includes a first doping region, a second doping region and a channel region disposed between and connects to the first doping region and the second doping region, and overlapping with the floating gates.