3D Semiconductor Memory Vertical Stacking Integration Density
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Solution Overview
Problem
Two-dimensional semiconductor memory devices face limitations in increasing integration density and cost due to challenges in forming fine patterns, requiring high-cost equipment and having restricted process technology improvements.
Innovation Solution
A three-dimensional semiconductor memory device is developed with a structure featuring conductive electrode patterns and insulating patterns alternately stacked on a substrate, including grooves on the sidewalls where data storing layers and active patterns are formed, allowing for increased integration density and reduced fabrication costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional semiconductor memory devices are used to increase integration density, then more memory cells can be packed in a planar area, but the minimum feature size and process technology limitations prevent further improvement and require high-cost equipment
Solution Approach 1:
The patent transitions from two-dimensional planar memory cell arrangement to three-dimensional vertical stacking of memory cells. Multiple electrode structures are stacked vertically on the substrate, with active patterns extending in grooves on opposite sidewalls. This vertical dimension allows significantly higher integration density without requiring smaller feature sizes or more complex planar patterning processes.
2Manufacturing precision
If fine patterns are formed to increase integration density in two-dimensional devices, then more cells fit in the planar area, but high-cost equipment is required and fabrication costs increase
Solution Approach 1:
By moving to three-dimensional vertical stacking, the patent achieves high integration density using relatively larger feature sizes that can be formed with existing, less expensive fabrication equipment. The vertical extension of active patterns in grooves on sidewalls of electrode structures allows density improvement without requiring advanced fine-patterning processes.
Solution Approach 2:
The memory device is segmented into multiple electrode structures stacked vertically, each containing memory cells formed with relatively larger features. This segmentation into vertical units allows each segment to be fabricated with standard process capabilities while the overall integration achieves high density through stacking.
3Quantity of substance
If two-dimensional semiconductor memory devices are highly integrated, then storage capacity increases, but the planar area occupied by each unit memory cell directly limits further integration
Solution Approach 1:
The patent stacks multiple electrode structures vertically on the substrate, with each electrode structure containing memory cells formed by active patterns in grooves on opposite sidewalls. This vertical three-dimensional arrangement allows many memory cells to occupy a small planar footprint, dramatically increasing storage capacity without proportionally increasing the chip area.
Data Source
AI summary
A three dimensional semiconductor memory device includes an electrode structure having a plurality of conductive electrode patterns and insulating patterns alternatingly stacked on a substrate. Opposite sidewalls of the electrode structure include respective grooves therein extending in a direction substantially perpendicular to the substrate. First and second active patterns protrude from the substrate and extend within the grooves in the opposite sidewalls of the electrode structure, respectively. Respective data storing layers extend in the grooves between the conductive electrode patterns of the electrode structure and sidewalls of the first and second active patterns adjacent thereto. Related fabrication methods are also discussed.