3D Memory Staircase Formation with Fewer Trim-Etch Cycles
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Planar memory cells face density limitations and high fabrication costs as feature sizes approach a lower limit, and existing multi-cycle trim and etch processes for 3D memory devices suffer from low throughput and high expense.
Innovation Solution
A method for forming a staircase structure in 3D memory devices involving the formation of alternating dielectric layer pairs, patterning a mask stack, and performing etch-trim processes to create multiple levels of staircase regions, reducing fabrication complexity and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing multi-cycle trim and etch processes are used to form staircase structures, then electrical connections for memory cells can be established, but fabrication complexity and manufacturing cost increase significantly
Solution Approach 1:
The patent divides the staircase formation process into multiple discrete etch steps, each creating a specific level or tier of the staircase structure. By segmenting the overall formation process into manageable stages with intermediate planarization steps, the complex multi-cycle trim and etch process is broken down into sequential, controllable operations that reduce cumulative complexity while maintaining connection reliability.
Solution Approach 2:
The patent performs preliminary planarization steps before final staircase formation to pre-establish a flat surface foundation. This preliminary action ensures that subsequent etching operations start from a uniform baseline, reducing the need for corrective trim cycles and simplifying the overall process while guaranteeing reliable electrical connections at each staircase level.
2Reliability
If existing multi-cycle trim and etch processes are used to form staircase structures, then electrical connections for memory cells can be established, but manufacturing cost increases significantly
Solution Approach 1:
The patent combines multiple trim and etch operations into integrated process modules where planarization, etching, and trimming are merged into sequential workflow blocks. By merging these operations with intermediate measurement and control steps, the total number of discrete process cycles is reduced, lowering manufacturing cost while preserving the reliability of electrical connections through maintained process precision.
Solution Approach 2:
The patent optimizes process parameters such as etch depth, trim amounts, and planarization thickness to achieve the desired staircase geometry in fewer cycles. By carefully controlling and adjusting these parameters, the process reduces the number of repeated trim-etch cycles needed, thereby reducing material waste, process time, and overall manufacturing cost while ensuring reliable electrical connections.
3Reliability
If existing multi-cycle trim and etch processes are used to form staircase structures, then electrical connections for memory cells can be established, but throughput decreases
Solution Approach 1:
The patent implements continuous planarization and etching operations without complete process interruptions between staircase level formations. By maintaining continuous useful action through overlapping process windows and eliminating idle time between cycles, the throughput is significantly improved while the reliability of electrical connections is preserved through consistent process execution across all staircase levels.
Solution Approach 2:
The patent employs periodic measurement and adjustment cycles embedded within the continuous fabrication process. Rather than stopping completely between etch cycles, periodic monitoring and controlled adjustments are made inline, allowing the process to maintain high throughput while ensuring each staircase level achieves the precise geometry needed for reliable electrical connections.
Data Source
AI summary
A method for forming a staircase structure of 3D memory, including: forming an alternating layer stack comprising a plurality of dielectric layer pairs disposed over a substrate; forming a first mask stack over the alternating layer stack; patterning the first mask stack to define a staircase region comprising a number of N sub-staircase regions over the alternating layer stack using a lithography process and N is greater than 1; forming a first staircase structure over the staircase region, the first staircase structure has a number of M steps at each of the staircase regions and M is greater than 1; and forming a second staircase structure on the first staircase structure, the second staircase structure has a number of 2*N*M steps at the staircase region.